SoC designers that adopt the UVM methodology will be able to design and verify more rapidly, once you've come up to speed with the UVM concepts. I've used the Aldec simulator before while teaching Verilog classes for TM Associates and it was easy for me to learn after previously using the ModelSim simulator from Mentor Graphics.
Using the UVM 1.1d library inside of Aldec's simulator, called Riviera-PRO, you'll be able to see at DAC:
- The latest UVM library
- Graphical debugging features
- Transaction visualization
- Class visualization
- Multi-clock assertion display
- The product roadmap for the future debugging enhancements
If you prefer to read the UVM 1.1 User Guide, the PDF download is here. The class library code for 1.1d can be downloaded as well in a .tar.gz file format, which also includes the UVM User Guide in PDF format.
With UVM there's a concept of your verification environment:
You can break up the verification task into components:
The actual UVM class hierarchy looks like:
The UVM methodology uses Transaction-Level Modeling (TLM) to communicate between your SoC which is the Device Under Test (DUT) and your test benches. The simplest example of TLM communication lets one component put a transaction to another:
The UVM User's Guide has 198 pages, organized into 8 chapters:
- Transaction-Level Modeling
- Developing Reusable Verification Components
- Using Verification Components
- Using the Register Layer Classes
- Advanced Topics
- UBus Verification Component Example
- UBus Specification
Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs.
With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.