Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its intent to acquire the IP business of Evatronix SA SKA, adding to its rapidly expanding IP offering. Based in Poland, Evatronix delivers a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, Display, MIPI, and storage controllers, which are highly complementary to Cadence’s IP offering.
- Evatronix is an established provider of USB, MIPI, display and storage controller IP with a broad customer base of approximately 600 customers.
- Nearly 200 USB controllers licensed to customers, including several top-tier semiconductor companies.
- Evatronix’s controllers, combined with PHYs from Cadence, will enable a complete interface IP solution that combines controller, PHY, verification IP and integration kits.
“The rapid innovations in the mobile, connectivity and cloud markets are driving today’s IP marketplace,” said Martin Lund, senior vice president of research and development, SoC Realization Group. “Evatronix’s IP products will boost Cadence’s offering for these segments, with high quality leading-edge IP that is production-proven.”
Evatronix co-founder and president Wojciech Sakowski said, “Evatronix’s IP cores and services are designed for ease-of-integration, quality and time-to-market. As part of Cadence, we will be able to reach more customers globally and to accelerate our IP roadmaps. The integration with Cadence will allow our customers to get to market faster with less effort.”
The acquisition is expected to close in the second quarter of 2013, and is not expected to have a material impact on Cadence’s balance sheet or second quarter or fiscal 2013 results of operations. Terms of the transaction were not disclosed.
More to see on: http://www.evatronix-ip.com/
On my side I am polishing the presentation I will make in the Design and Verification IP tracks. This year is the first with a special attention about IP and Verification IP: PCIe and M-PHY, USB 3.0 PHY IP, Memory Models for Verification and DDR SDRAM Memory Controller and PHY IP, and the related Verification IP with a presentation from Susan Peterson from Cadence. It will also be a good opportunity to learn about Tensilica Dataplane CPU and I am sure not to miss that track, as I will make the presentation just before, named “Interface IP protocols: the winners, the losers in 2012”. It will be strongly updated from the presentation made during IP-SoC last December in Grenoble, as many changes have occurred during Q1 2013! Because we can now take into account the 2012 actual IP sales results for the various protocols (DDRn, USB, PCIe, SATA, MIPI, Ethernet, Thunderbolt, HDMI, DP), it will be fresh information, in advance from the launch of the “Interface IP Survey”…
Eric Esteve from IPNEST