Today's complex SOC design is driven by the constant demand for high performance capabilities, rich feature sets, concurrency modes and low power requirements. This creates many challenges in delivering on what users want from their devices and these challenges impact the whole SOC eco-system from Design, analysis, sign-off, reliability and time to market. These trends will continue to challenge SOC designers in the future especially now that compute and mobile devices are merging.
My talk will focus on the key challenges that designers are facing especially in key areas like performance, power, thermal and reliability and discusses some of the future trends in the industry that requires a more efficient model between foundries, SOC designers and EDA companies.
Charles Matar is a Vice President of Engineering at Qualcomm. He joined Qualcomm in 2003 and formed a new CPU team the delivered ARM based CPU Cores for Qualcomm's Mobile SOCs. After that, he was the chip lead that delivered the first 65nm Mobile SOC in 2007 and then he went on to manage the Physical Design Team, Low power Implementation team, Serdes and the foundation IP Design. His responsibility then included delivering all of the SOC tape outs for San Diego's QCT division and enabling new technology nodes for next generation SOCs like backend infrastructure, IP, methodology and working closely with foundries, design and EDA companies. Presently, he is managing the Graphics Hardware team in Qualcomm responsible for delivering all of Qualcomm's Adreno GPU cores.
Prior to joining Qualcomm, Charles held multiple positions as a CPU designer and manager. His technical interest is in SOC and Processor Design, Low Power Design and Process Technology.
Charles Matar hold a BSEE from the University of Texas at Austin and an MSEE from Southern Methodist University.
Charlie will be followed by technical tracks/breakout sessions featuring application specific presentations focused on 20-nm low-power designs and high-speed I/O verification. They will include presentations by leading companies such as Samsung-SSI and Texas Instruments sharing their experiences designing for low-power applications.
The 20nm Low-Power IC Design track will discuss tools and methodologies that address power and reliability challenges for advanced low-power designs. For those designing high-speed I/O interfaces such as DDR3/4, a special technical presentation entitled "Chip-Package-System (CPS) Methodology for Giga-hertz Performance Mobile Electronics" should be of key interest.
View the full Agenda and Technical Track abstracts.
For more information on the series.
Reserve Your Seat Today!
I will see you there!