Q: Tell me about the history of Novocell and how it got started.
A: We are a spin-offf from a 1995 memory design company, David Novosel (ex TI, ST, Motorola) created Intelligent Microdesign and was a consultant, then started up Novocell to specialize in OTP in 2001. David was my uncle however he died in 2009.
Q: According to your LinkedIn profile you played pro sports, what team?
A: Out of college I played baseball for the Arizona Diamondbacks as a pitcher.
Q: How big is Novocell Semi?
A: We are 10 people and hiring, located in Hermitage, Pennsylvania.
Q: How do IC designers find out about OTP from Novocell?
A: Over the years we've developed fab relationships to prove the technology, then fabs recommend Novocell to their customers. The fabs include: TowerJazz, TSMC, IBM, UMC, GLOBALFOUNDRIES, SilTerra.
Q: What is unique about your OTP approach?
A: Our OTP technology can support any standard CMOS process, no special layers are needed, so it is really fab independent.
Q: What kind of SOCs use your IP?
A: OTP is used in so many places. Analog market for trimming power sequences, trimming a MEMS device. Memory redundancy. Fuse replacement. Security applications, RFID code storage. Boot codes for processors. Configuration of a device by enabling features. 22 uses in a cell phone could use OTP IP blocks. Automotive sensors, calibrations. Set top boxes, codes.
Q: What kind of IP products does Novocell offer?
A: Three categories of IP: NOVObits (8bits to 512 bits), NOVOBytes (512bits to 32kbits) and NOVOHD (16Kbits to 4Mbits).
Q: How long would it take to qualify your OTP IP for a new process node?
A: It takes about 1.5 to 2 months to tapeout our IP for a new node.
Q: How do you license your IP?
A: There's a small usage fee up front, then backend royalties. The fab can also license the technology directly to the SoC customers. You also can do a royalty buyout.
Q: Who do you compete with?
A: Kilopass is the main competitor, and with their approach you have to route a special high voltage signal around the chip. Novocell instead uses the chip internal supply values and creates a high voltage only across the anti-fuse, so it's not routed around the chip. The Novocell approach senses the breakdown event and monitors when to turn off the OTP programming.
Q: How many different IC designs do you complete each year?
A: We have about 50 client projects per year. Our focus is a standard IP off the shelf. We can do our design work within a few days.
Q: What technology nodes do you design your IP for?
A: Back in 2000 we did OTP designs with LSI and TSMC at .25 micron and .35 micron. Our first customer tapeout was a 1st time success, and there was no tweaking required. Recently we just completed a 45nm tapeout and are now designing at more advanced nodes too.
Q: What EDA tools do you use when designing your OTP IP?
A: Our IC designs are mostly transistor-level and we are using:
- Tanner T-SPICE for circuit simulation with W-Edit for waveform viewing
- Tanner schematic and layout: S-Edit and L-Edit
- Tanner DRC: HiPer Verify for smaller blocks
- Mentor DRC: Calibre for larger blocks
- Verilog simulation: Cadence
- Logic synthesis
Q: How long have you been using Tanner EDA tools?
A: We started using Tanner tools in 2004/2005 time frame, and before then were using Cadence tools.
Q: Why did you choose Tanner tools?
A: Tanner provided better pricing for our start-up company, and it was the best value, plus they did have a nice IC design package. We are all transistor-level, mixed signal, small digital. Tanner EDA is well supported by the foundries for SPICE and DRC decks, support has been great at keeping SPICE models up to date. Evaluation time was only about 1-2 months, support was by phone, training was in person.
Q: How do you protect your IP?
A: We had three core patents when the company was founded, then four more issued, and about 12 total applied for. Patents granted to David Novosel include:
Q: What will success look like for Novocell one year from now?
A: More market share, more customers, more design wins. Our focus is to make OTP a drop-in solution for IC designs.