The theme of the theater presentation was “right here, right now” to reflect the fact that RealTime Designer is…err…real. As is Oasys themselves, having just had a cash injection from the #1 semiconductor company and the #1 FPGA company. That would be Intel Capital and Xilinx.
Oasys are proud of their customer list too. Qualcomm, Netlogic (now part of Broadcom), Texas Instruments. With Xilinx and Intel Capital they have relationships with the top US semiconductor companies. After all if companies like these are doing their most challenging designs with Oasys then that is a true vote of confidence in the technology. It is really hard to tell if an engine is any good just by taking the cylinder-head off, much easer to see who is confident enough to put the engine in their cars.
RealTime Designer’s big claim to fame is that it is blazingly fast and has huge capacity. Traditional synthesis takes in RTL and converts it to a rough-and-ready netlist and then optimizes that netlist. This requires the whole netlist to be in memory (so needs a lot of it) and means that only small incremental improvements are possible. Thus to get anywhere, it needs to make millions of these little changes which takes a long time. RealTime Designer operates by partitioning the RTL into small regions and each reducing each of those to a fully-placed netlist. If the design doesn’t make its constraints (paths with negative slack, meaning the netlist is too slow) then it returns to the RTL level, repartitions (if appropriate), resynthesizes and re-places just that small regions and perhaps its neighbors. This turns out to converge must faster on a solution with good quality of results (QoR) requiring only thousands of adjustments.
As a result RealTime Designer has a capacity of over 100M gates and runs 5-40 times faster than traditional synthesis tools.
The demo on the show floor didn’t actually run RealTime Designer live (most of the time) since most people don’t even have the patience to watch a 15 minute demo and presentation. But when they did that’s all that the design they used for the demo took to synthesize. How big was it? It was a full-chip 6 million gate quad-core SPARC T1, 421 macros, 261 I/O pads, 1.2GHz clock in 65nm.