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Tag: eda

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  1. EDA Machine Learning from the Experts!

    Published by Daniel Nenni, 3 Days Ago 05:00 AM
    • Comments: 5
    Last Post: 4 Hours Ago 01:15 AM
    by simguru 
    • Comments: 2
    Last Post: 11-01-2016 09:02 AM
    by Mitch Heins 
  2. CTO Interview: Peter Theunis of Methodics

    Published by Daniel Nenni, 02-06-2017 05:00 AM
    • Comments: 0

    CMS:
    Methodics

  3. 65nm to 45nm SerDes IP Migration Success Story

    Published by Daniel Nenni, 05-25-2011 01:43 PM
    • Comments: 4
    Last Post: 06-01-2011 01:53 AM
    by harpoon 

    CMS:
    Sagantec

  4. Adjusting Custom IP to Process Changes

    Published by Daniel Nenni, 05-16-2011 11:57 AM
    • Comments: 12
    Last Post: 05-19-2011 07:30 AM
    by admin 

    CMS:
    Sagantec

  5. DAC 2012 Cheerleader Controversy!

    Published by Daniel Nenni, 07-08-2012 07:00 PM
    • Comments: 16
    Last Post: 07-16-2012 04:22 PM
    by Daniel Nenni 

    CMS:
    Events

  6. New Remote Access Standard

    Published by Paul McLellan, 08-02-2013 08:13 AM
    • Comments: 11
    Last Post: 08-09-2013 12:28 PM
    by Frank Wiedmann 

    CMS:
    Zentera

  7. SoC Optimization Using FPGA Prototyping

    Published by Daniel Payne, 05-18-2013 09:00 AM
    • Comments: 0

    CMS:
    Tektronix

  8. The TSMC OIP Technical Paper Abstracts are up!

    Published by Daniel Nenni, 08-25-2013 06:10 PM
    • Comments: 0

    CMS:
    TSMC

  9. 12m FPGA prototyping sans partitioning

    Published by Don Dingee, 10-16-2012 07:30 PM
    • Comments: 1
    Last Post: 10-24-2012 02:46 AM
    by ChachraVijay 

    CMS:
    Aldec

    • Comments: 0

    CMS:
    Solido

  10. A Brief History of TSMC's OIP part 2

    Published by Paul McLellan, 09-18-2013 09:00 PM
    • Comments: 1
    Last Post: 09-22-2013 07:54 AM
    by LinkedIn 

    CMS:
    TSMC

  11. A Brief History of TSMC OIP

    Published by Paul McLellan, 09-01-2013 07:00 PM
    • Comments: 0

    CMS:
    TSMC

  12. Avoiding layout related variability issues

    Published by Daniel Nenni, 05-26-2013 05:55 AM
    • Comments: 2
    Last Post: 05-31-2013 12:09 PM
    by Daniel Nenni 

    CMS:
    Sage DA

  13. Sage Design Automation iDRM Launch

    Published by Daniel Nenni, 05-07-2013 05:00 PM
    • Comments: 0

    CMS:
    Sage DA

  14. FinFET Modeling and Extraction at 16-nm

    Published by Daniel Payne, 12-18-2012 10:05 AM
    • Comments: 4
    Last Post: 12-19-2012 09:58 AM
    by LinkedIn 

    CMS:
    Synopsys

  15. Aldec-Altera DO-254

    Published by Daniel Nenni, 09-25-2012 07:58 PM
    • Comments: 0

    CMS:
    Aldec

    • Comments: 0

    CMS:
    ICScape

    • Comments: 0
  16. iPDKs and Analog Constraints

    Published by Daniel Payne, 06-13-2011 03:09 PM
    • Comments: 2
    Last Post: 06-21-2011 04:37 AM
    by Staf_Verhaegen 

    CMS:
    Synopsys

  17. Getting Real Time Calibre DRC Results

    Published by Daniel Payne, 03-10-2011 08:00 AM
    • Comments: 11
    Last Post: 04-27-2011 09:25 AM
    by Daniel Payne 
  18. New ERC Tools Catch Design Errors

    Published by glforte, 02-11-2011 12:18 PM
    • Comments: 3
    Last Post: 02-28-2011 07:45 AM
    by admin 
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