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iDRM: Fixing the broken interface between design and manufacturing


What are Design Quality Checks and who needs them?

Today’s DRC decks are made by the foundries representing each foundry’s own knowledge of its process limitations as can be affected by physical design. The foundry’s view is design-agnostic: it does not make assumptions on design goals, but rather is focused on keeping the minimum design rules that ensure no obvious yield issues are created.

Many design organizations have a broader and more complex view of physical design objectives, based on their specific product, specific design style and specific design goals and experience. Typical examples are: designers of analog and mixed-signal devices, high performance or low power products, custom circuits, logic libraries and custom IP designers.

Each such design organization can have a set of specific guidelines and additional considerations that they need to observe in physical design to minimize variability, ensure specific power and performance goals and avoid issues that are specific to their product and design style. “Design Quality Checks” refers to all such custom rules and checks that may be added as an additional layer of rules and checks by a design organization, formalizing their collective experience and knowledge of what it takes to achieve high quality physical design for their product space.

These design organizations need a quick and automated method for both capturing such rules clearly and formally, as well as implementing them as checks for their physical design team. iDRM with its GUI based, no-programming rule capture enables designers and CAD teams to quickly define and capture design quality rules and automatically create correct-by-construction checks for them.
Defining each rule takes only a few minutes and does not require any programming:
  • you draw the layout example you are interested in (or clip it from existing layout)
  • you add parameters to the drawing: e.g. distances, widths, separations, etc. and give them names
  • You write an expression using these parameters to define the required rules.

That’s it: the rule is defined and the check is ready to use!

Data mining and statistics

Once a specific topology or rule is captured, iDRM can scan through the layout of a block or complete design and find all instances that use that topology and take all the relevant measurements of the parameters (variables) that were used in the rule definition. The result is a complete and dynamically sort-able list of all such instances, each with complete information of the relevant measurements, orientations, location, etc.

iDRM can present the results in tables, various graph formats (e.g. 1d histograms, 2d occurrence graphs, Pareto charts, etc.), or export them to a spreadsheet. The user can dynamically switch between different views, filter data and zoom in to areas of interest. An integrated layout viewer provides a one-click hop from each table or graph entry to the layout locations where this specific set of values is found.

Using layout data mining, users can get valuable complete and accurate quantitative information on all layout features, patterns and devices, looks for value distributions or focus on specific values such as unexpected outliers.

Use case examples:
  • For all MOS devices: measure the distances from the gate to the diffusion contacts: this provides a quick overview of SD resistance for all devices.
  • Measure all distances from the gate to the well edge and calculate the WPE impact for each
  • Get LOD (length of diffusion) measurements for all devices (a factor in device stress)

The WPE and LOD statistics can quickly show if all devices are in the expected range and outliers can be immediately identified and further investigated.
  • Classify all PMOS and NMOS devices, by diffusion shape, poly shape and measure all Ws and Ls
  • Get all distances from via cuts to an external metal edge – these affect reliability caused by time-dependent dielectric breakdown (TDDB).
  • Measure distances on critical rules, e.g. all line-end enclosures for each via
  • Check for patterns and rule values which may hinder process migration or a rule change, and

  • check distances if there is sufficient slack to accommodate such changes

  • and many more…

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