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Thread: Moore's Law is not ending just transforming

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    Admin Daniel Nenni's Avatar
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    Moore's Law is not ending just transforming

    We received a lot of positive feedback from a recent note we wrote regarding the semiconductor industry becoming more memory centric again. We also talked about some fundamental changes in the industry which both underlie and drive the changes. In this note we take a further look at these changes, what they mean and who can benefit and therefore which stocks may benefit.

    The "Soul" of the semiconductor industry is Moore's Law (or perhaps more accurately..observation) that transistor density is doubling every two years. This has been as much an economic law as physical law , performance law all rolled into one. The "yardstick" used to measure Moore's Law and its progress has always been transistor pitch (the critical dimensions of a transistor) in a simple planar measurement, because the industry only thought in two dimensions. Moore's Law could thus be proven to have a finite limit as you can't cut atoms in half and still have them work as intended. The practical limit of Moore's Law occurs sooner as "spooky" materials effects show up long before we get to single atoms (even though the industry has done a very good job of keeping these effects at bay...)

    The Soul of a New Machine.... Maire's Maxim...

    "As semiconductor planar technology approaches the finite limits of transistor pitch, vertical scaling & design scaling will offset planar limitations allowing continued linear price/performance improvements"

    Moore's Trans Migration
    Transmigration is "the movement of the soul into another body after death ". Moore's Law will live on after the current body of planar transistor pitch improvements dies. 3D structures such as VNAND and die stacking, 2.5D & 3D packaging are driving the third dimension into the semiconductor industry. Multi core and AI designs are driving design scaling. Taken together they will offset any slowing of Moore's progress as pitch scaling comes closer to the end.

    Measuring transistors per cubic mm rather than square mm...
    As we had mentioned in our last note the industry has yet to switch to the new metric of cubic transistor density rather than transistors per square mm. Its hard to get 50 years of measurement to change let alone even recognize the need for change. Sooner or later someone will figure out the cubic transistor density of VNAND and publish that number. In the mean time we can think of non leading edge transistor pitch multiplied by 128 layers of transistors minus some real estate for the staircase. It feels like it has to be at least a 50X improvement. The vertical scaling of VNAND is likely equivalent to several generations of planar scaling beyond the current known physical limits transistor pitch. This suggests that VNAND is already living in the afterlife of planar technology....

    Vertical Scaling - "To infinity and beyond...."
    You can always add another layer but you can't keep cutting transistor sizes in half forever (see "Zeno's Paradox"). This is almost true as adding more layers does get harder and there are likely practical limits much as there are practical limits on how many stories high a building can go. But the limits are obviously beyond how small you can make a room in a building or how small you can make a transistor.

    The other way of going vertical is 2.5D and 3D packaging which is akin to how many double wide trailers can you stack on one another. Perhaps a vertical trailer park not as elegant as the high rise apartment of VNAND but it is effective in the end result of density.

    Who benefits from vertical scaling
    The enabler of planar scaling has always been lithography to make finer and finer pitches. The enabler of vertical scaling is dep and etch which adds and defines the multitude of layers. Right now the leading and defining edge of vertical scaling is defined by a very difficult, badass, "drill and pray" , HARC (High Aspect Ratio Contact) etch that Lam dominates. Staircase etch and deposition have grown as well so we have seen both AMAT and TEL (Tokyo Electron) strongly benefit as well. These new vertical structures are a bit of a nightmare and certainly require much metrology thus benefitting KLAC, NANO & NVMI.

    TEL Tells the same great story
    Yesterday TEL had an investor update which in essence repeated the same positive news heard from Lam and AMAT and the rest of the industry. There was an excellent presentation that was chock full of facts and information about the current strong up cycle.

    Tokyo Electron IR Presentation Link

    Slide 26 of this presentation tells the story of who benefits from VNAND and who loses. The slide shows etch more than tripling its share of VNAND spend from under 15% to over 50%, with deposition close to doubling. As we have pointed out previously, litho is the biggest loser of VNAND spend share seeing spending share dropping by two thirds as compared to planar. This clearly translates to the financial performance we have seen.

    TEL has the extra benefit of higher exposure to 2.5D & 3D as compared to others. We would expect that Lam and AMAT should increase their exposure to these back end processes.

    I'm all about that NAND, bout that NAND, no logic......
    As we have pointed out in previous articles the industry has become much more memory centric in somewhat of a return to its roots. The obvious beneficiaries of the memory renaissance are Samsung, Toshiba and Micron. We have high hopes for Intel's XPoint and are somewhat disappointed by the slow progress and information flow. The limitless demand for non volatile storage will continue to drive capex spending on memory for the near term. We are seeing a good uptick in spending both in 2016 and 2017 and initial views on 2018 look good as well. If VNAND were out of the equation we would likely be down and at best flat as logic has been lame and foundry cycles with IPhone node changes.

    From a stock perspective we still like MU as we don't see any near term change in the current positive dynamics

    The economic "trickle down" impact
    If Lam, AMAT & TEL are doing so well, obviously their suppliers are also seeing good times. These include AEIS, MKSI, ICHR, UCTT and others. Both ICHR and UCTT have the most direct benefit as they are most exposed. From a stock point of view these are obviously more highly leveraged to the same industry dynamics as their customers.

    Design scaling... More cores....
    In addition to the vertical scaling we see in memory, design scaling will also add gains that will offset declines in pitch scaling. It is interesting to note that Intel just released an 18 core processor at the top of its product line. The industry obviously ran up against a speed limit in single processors cores as we reach power/heat issues related to scaling so we continue to increase core count as an alternate way of increasing compute power in a single die.

    Its not your fathers 4004
    A lot has changed but a lot has also not changed in CPU architecture since the first Intel 4004 back in 1971 that sported 2300 transistors at 10 micron pitch. We see the rapid rise of AI processors, Graphic processors and other specialty devices as a way of getting more out of the same amount of silicon by designing application specific architectures that are much more silicon efficient than general purpose CPUs as they can remove unneeded transistors and add transistors where needed.

    This type of "design scaling", to get more performance out of the same amount of silicon while not increasing die size or transistor count gives us similar price/performance increases as Moore's Law would otherwise get by pitch scaling a generic CPU.

    To us this means that both of Moore's Law progress measurements "bragging rights" of transistor pitch and transistor count need are outdated and need to be retired (Sorry Intel....), as they are no longer the ultimate indication of semiconductor performance.

    From a stock & company perspective, both Apple and Google are leaders in AI silicon. Google has its "Tensor Processing Unit" and Apple has a "Neural Engine".

    Given the huge advancements Apple has made with its "A" series processors and its highly efficient cell design we think they could make huge advances. Google has already reported a 15 to 20X improvement in processing speeds with its TPU. Intel needs to step up its game in this area as its technology lead is based on both pitch scaling and generic processors, both of which are in decline. Intel obviously has some upside in communications specific processors an area where it has done well.

    Show me the money....
    The cost of transistor pitch scaling has gone bonkers as the lack of EUV has driven the industry to quad patterning and beyond as well other "unnatural" acts to keep progress on track. By comparison, vertical scaling, especially through 2.5D and 3D package scaling is much less expensive. Improvements through design scaling not only offer better performance but a lower cost of implementation as compared to more generic solutions. Given that the fundamental impact of Moore's Law is an economic one, the lower cost of alternative scaling solutions as compared to transistor pitch scaling is right in line with Moore's core tenet.

    Stocks and Summary
    Investors need to retune their semiconductor investment criteria to account for the reincarnation of Moore's Law as pitch scaling, generic processors in a logic centric world fades into oblivion and three dimensional & application specific silicon lead in a memory driven environment.

    This obviously will not happen overnight but we have seen some relatively rapid changes over the last year alone....just look at the stocks....they look like have been reincarnated into a new world of demand.

    Stocks we like are; MU, AMAT, LRCX & KLAC...in smaller cap MKSI, ICHR... On a relative basis we think we will see underperformance from INTC and ASML.

    Reference: Moore's Law is not ending just transforming - New opportunities are created by new solutions - Who will own the new Moore's Law era?

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    What is Moore's Law? Specifically, how is it defined? Based on one definition it's dead, but redefine it and it will live forever.

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    Quote Originally Posted by mgsporer View Post
    What is Moore's Law? Specifically, how is it defined? Based on one definition it's dead, but redefine it and it will live forever.
    To be clear, Moore's Law was an observation made by Gordon Moore. It is not bound by the laws of physics and is open to interpretation. So it will never be dead per say....

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    Two thoughts.

    1. Science and Engineering at the University level in America is a disaster. Too many professors and lecturers that don't care if their students reach their potential or not. At the corporate level it's worse.

    2. Engineering is spread too thin with Search engines, ecommerce, cell phones .... there isn't the talent that use to be. What I mean is intel and amd don't have the pick of the talent like they use to.

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    "Ice Lake successors have reached the ‘tape-in’ stage."

    Hopefully they mean tape-out?

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    5 signs you might be in denial about Moore's Law ending
    - You come up with new definitions of scaling (redirecting)
    - You point out how great the new scaling is (minimizing)
    - You blame the victims
    - You keep a short-term focus (nothing to see here, move along everyone)
    - You present the limited good news (VNAND!) in isolation from the overall bad news

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    benb, i agree with you.

    The economics of moore's law we're pretty simple: how many transistors you could make in a single machine pass. How many ? exponentially more. And they had a long horizon - until atoms refuse to cooperate. Decades.

    But 3D scaling ? meh. sure there are some savings , but basically, if you want more transistors, you need another pass at the machine. and those savings, for logic, stop quite fast.

    But the good news: we have no choice but build custom accelerators. so that's a lot of work. And they often give great results.And the other good news: quite often , older process are more optimal for cloud computing:

    http://cseweb.ucsd.edu/~mbtaylor/pap...2017_final.pdf

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