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Thread: Samsung 7LPP a "2nd Gen" 7nm

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    Samsung 7LPP a "2nd Gen" 7nm

    VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM – WikiChip Fuse

    This WikiChip fuse article which appeared several days ago is a pretty nice short review of Samsung's 7nm presentations from both VLSI 2018 and ISSCC 2018. It also seems to provide a pretty balanced look at Samsung's 7nm situation. Most of the VLSI 2018 stuff was covered here at SemiWiki already. So I'll just list a number of points from the 5-page article, many probably already known:

    1. Samsung referred to 7LPP as the "2nd generation" 7nm, the first being 7LPE, which practically never happened but was developed at one point.

    2. Fin pitch 27 nm, Gate pitch 54 nm, Metal pitch 36 nm.

    3. EUV single exposure for contact, metal, >25% mask reduction consequently. (Note: previously EUV for fin layer has been corrected)

    4. 6.75 tracks for high density standard cells and 7.5 tracks for high performance standard cells. High-density cell 112.79 MTr/mm2.

    5. A reported advantage of EUV was "pattern fidelity." This is only applicable to nonlinear 2D patterns, and can be attributed to high k1.

    6. Another reported advantage of EUV was bidirectionality, or the use of 2D patterns. This allows serial via reduction, and less IR drop. However, as we know from many analyses, they can only keep this benefit for sufficiently large pitches. Ironically, the 7LPP EUV designs actually looked more like 1.5D while the triple-patterned 10LPP looked like 'true' 2D.

    7. They reported a very tight CD distribution (1nm 3s) which looks like a very high dose (>50 mJ/cm2) being used (literature reports 3-4 nm 3s at 50 mJ/cm2 or lower). The dimension also looks pretty large, most likely 2x-nm scale since there was comparison with SADP.

    8. Other tricks to enhance density include special constructs (T-shape, single dummy gate).

    9. Readiness assessment: official line is to ramp late this year through early next year, though unofficially it could delay to maybe even 2020. Different answers from different Samsung personnel. Mask inspection still not ready, as well as photoresist. No pellicles used for now because of low transmission. Without many pieces ready, Samsung's position looks highly experimental, as if they are playing guinea pig. But during this time, 8LPP, the backup basically, has much in common with 7LPP.

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    Last edited by Fred Chen; 4 Weeks Ago at 12:52 PM.
     

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    Fred
    I think there is some confusion on whether this process represents 7LPP. I think this paper presented features which will be employed in the 5LPE process like SDB.

    https://www.semiwiki.com/forum/conte...dry-forum.html

    I think 7LPP will likely be in HVM by late 2019 or early 2020.

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    Quote Originally Posted by raghu78 View Post
    Fred
    I think there is some confusion on whether this process represents 7LPP. I think this paper presented features which will be employed in the 5LPE process like SDB.

    https://www.semiwiki.com/forum/conte...dry-forum.html

    I think 7LPP will likely be in HVM by late 2019 or early 2020.
    Thanks for bringing that up. It's a shame but maybe not surprising that the process names are not so firm. The article referenced the speaker himself and had a process comparison table as well, which I did not include directly because I hadn't requested permissions yet. But the key thing is, except for single diffusion break, 2nd generation 7nm has the same FEOL updates as 8LPP.

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    Last edited by Fred Chen; 4 Weeks Ago at 05:27 PM.
     

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    Blogger Scotten Jones's Avatar
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    I was surprised by your saying they use EUV for fins.

    I have both of the papers you mention and I went back and looked at them, I see no indication in the papers they use EUV for fin, in fact the VLSIT paper specifically says they use EUV for MOL and BEOL and doesn't say FEOL.

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    Quote Originally Posted by Scotten Jones View Post
    I was surprised by your saying they use EUV for fins.
    This is from David Schor at WikiChip. He most likely made an error. He did attend the conference, though.

    According to Akira Fukuda at PC Watch, they are using ArF immersion SAQP for fin patterning:

    【福田*のセミコン*界最前線】完 に近づいた、SamsungのEUVリソグラフィ 採用7nm半導体量産技術 - PC Watch

    Unfortunately, VLSIT 2018 papers are not online at IEEE Explore yet...

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    Blogger Scotten Jones's Avatar
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    Quote Originally Posted by carop View Post
    This is from David Schor at WikiChip. He most likely made an error. He did attend the conference, though.

    According to Akira Fukuda at PC Watch, they are using ArF immersion SAQP for fin patterning:

    【福田*のセミコン*界最前線】完 に近づいた、SamsungのEUVリソグラフィ 採用7nm半導体量産技術 - PC Watch

    Unfortunately, VLSIT 2018 papers are not online at IEEE Explore yet...
    Yes SAQP with ArFi is how I would expect fins to be patterned.

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    Quote Originally Posted by Scotten Jones View Post
    Yes SAQP with ArFi is how I would expect fins to be patterned.
    Yes, same here.

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    Quote Originally Posted by carop View Post
    This is from David Schor at WikiChip. He most likely made an error. He did attend the conference, though.

    According to Akira Fukuda at PC Watch, they are using ArF immersion SAQP for fin patterning:

    【福田*のセミコン*界最前線】完 に近づいた、SamsungのEUVリソグラフィ 採用7nm半導体量産技術 - PC Watch

    Unfortunately, VLSIT 2018 papers are not online at IEEE Explore yet...
    I have sent a question about it to wikichip, including this link, which is very helpful, thanks!

    Indeed the paper and conference preview does not explicitly mention any EUV FEOL patterning.

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    Quote Originally Posted by Scotten Jones View Post
    Yes SAQP with ArFi is how I would expect fins to be patterned.
    Yes especially since the limit of 2D EUV is 36nm and the fin pitch is 27nm.

    https://www.semiwiki.com/forum/conte...landscape.html

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    Quote Originally Posted by Fred Chen View Post
    Yes, same here.
    Why did you post that fins were done with EUV if you didn't believe it?

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    Quote Originally Posted by Scotten Jones View Post
    Why did you post that fins were done with EUV if you didn't believe it?
    I just reported what the article stated. Wikichip acknowledged my question so hopefully I can get the clarification on that soon. Although it's not what I expect, it looks like a deliberate EUV exercise primarily.

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    Quote Originally Posted by Fred Chen View Post
    I just reported what the article stated. Wikichip acknowledged my question so hopefully I can get the clarification on that soon. Although it's not what I expect, it looks like a deliberate EUV exercise primarily.
    I got the reply back from Wikichip's David Schor. He had interviewed the speaker WonCheol Jeong directly so there will be information not available from the paper, including pitches, which layers, etc. In the interview, Jeong mentioned 3 layers used EUV, one of which was the fin. For fear of mishearing, David will try to reconfirm at the next available conference opportunity (IEDM).

    Note: this has been corrected at Wikichip so that the fin is NOT done by EUV but by ArFi SAQP.

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    Last edited by Fred Chen; 4 Weeks Ago at 12:54 PM. Reason: updated correction
     

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    I also got permission to use figures, so here is a clip from the 7nm metal:

    Samsung 7LPP a "2nd Gen" 7nm-samsung-7nm-euv-m1-clip.jpg
    Source: VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM – Page 4 – WikiChip Fuse (David Schor's coverage of VLSI 2018 paper by W. C. Jeong et al.)

    Note that the AVERAGE metal line pitch is in fact much larger than the MINIMUM metal line pitch, and there is also a large range of pitches. This is a high risk for focus incompatibility from 3D mask effects as well as higher stochastic failure rate at larger pitches.

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    Last edited by Fred Chen; 4 Weeks Ago at 05:26 PM.
     

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