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Thread: Partial Issues about Integrated Circuit

  1. #1
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    Smile Partial Issues about Integrated Circuit

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    Cross clock domain signals, using two-level register structure to reduce meta-stability, The reason of meta-stability is that the setup time and hold time of register can not be satisfied because the input signal is out of sync with the clock, so the register can not output the correct and valid value. If it not a two-level register to synchronize the clock, such as multilevel register, what will happen?

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    Blogger Bernard Murphy's Avatar
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    I'm not sure I fully understand your question. This is one of the best sources on the whole topic and might answer your questions:

    http://www.sunburst-design.com/paper...Boston_CDC.pdf

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    I don't know how you think about this question, because I can't open the link you enclosed here.

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    I have read some material which related to it, such as integrated circuit. The meta-stability can not be completely eliminated, but the longer the time is (the multilevel registers are used), the lower the probability is. In other words, the meta-stability state will eventually become stable, and the longer the time is, the more stable it will be. In addition, the relation between the occurrence probability of meta-stability and the delay time is approximately exponential function. If the data value is read after a period of delay, the longer the delay time is, the lower the probability of meta-stability is. In the system of 100MHz, the relation between the generation probability and the delay is approximately:
    Partial Issues about Integrated Circuit-failure-probabilities-vs-delay-time.jpg
    But I still have problems with it. Anyone can give me more info about it.

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  5. #5
    Blogger Bernard Murphy's Avatar
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    Perhaps try accessing the link from a device outside your current network (maybe your phone or tablet?) I have no problem getting to the link, suggesting whatever network you are in may be blocking that URL for some reason

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    Blogger Daniel Payne's Avatar
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    Bernard,

    The link to the PDF document works just fine.

    Coming from a transistor-level IC design background, the issue of meta-stability has been known about for decades now, and with a SPICE circuit simulator you can measure it.

    Simulating Metastability in Digital Circuits Using Spice | Des Pudels Kern

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    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

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    Thanks a lot, I know the basic knowledge of metastability, what I want to know is the ratio of "stay" and "enter" metastability, and then to calculate the final result.

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