You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!




Page 1 of 2 12 LastLast
Results 1 to 10 of 19

Thread: NVIDIA announces Tesla GV100 GPU on TSMC 12nm FFN

  1. #1
    Member
    Join Date
    Jan 2017
    Posts
    23
    Thumbs Up
    Received: 9
    Given: 9

    NVIDIA announces Tesla GV100 GPU on TSMC 12nm FFN

    https://abload.de/img/2017-05-1020_22_23-20ubl6o.jpg

    12FFC has 1.2x the density and 25% less power / 10% higher perf. over 16FF+, but this is the first time I've heard of 12FFN. What do we know about this 16FF+ optimization?

    1 Not allowed!
     

  2. #2
    Admin Daniel Nenni's Avatar
    Join Date
    Aug 2010
    Location
    Silicon Valley
    Posts
    3,964
    Thumbs Up
    Received: 697
    Given: 1,990
    There is a discussion on 12nm here:

    https://www.semiwiki.com/forum/f2/ts...node-8689.html

    I also covered it in a blog here:

    https://www.semiwiki.com/forum/conte...m-7nm-euv.html

    Since NVDA is already on 16nm moving to 12nm is not a big challenge. From what I have heard NVDA will skip 10nm and move directly to 7nm HPC, which they co developed with TSMC.

    0 Not allowed!
    Now available in print or Kindle: "Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices"

  3. #3
    Top Influencer
    Join Date
    Aug 2014
    Posts
    373
    Thumbs Up
    Received: 157
    Given: 90
    According to Anandtech N stands for Nvidia.
    In terms of die size and transistor count, NVIDIA is genuinely building the biggest GPU they can get away with: 21.1 billion transistors, at a massive 815mm2, built on TSMC’s still green 12nm “FFN” process (the ‘n’ stands for NVIDIA; it’s a customized higher perf version of 12nm for NVIDIA).
    NVIDIA Volta Unveiled: GV100 GPU and Tesla V100 Accelerator Announced

    0 Not allowed!
     

  4. #4
    Member
    Join Date
    Jan 2017
    Posts
    23
    Thumbs Up
    Received: 9
    Given: 9
    NVIDIA now command such power that they can get a half-node tailor-made for them? Wow.

    0 Not allowed!
     

  5. #5
    Admin Daniel Nenni's Avatar
    Join Date
    Aug 2010
    Location
    Silicon Valley
    Posts
    3,964
    Thumbs Up
    Received: 697
    Given: 1,990
    I just got through the NVIDIA collateral and let me say, WOW, what an incredible run they are having. The question I have is who will catch them? Certainly not AMD or Intel.

    I am wondering about the inference stuff. NVDA seems to be chasing that market with GPUs but it seems like overkill to me. FPGAs seem much more suited. I do understand the single vendor approach to AI, one vendor for both learning and inference but on a chip vs chip level FPGAs seem much better suited. Thoughts?

    1 Not allowed!
    Now available in print or Kindle: "Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices"

  6. #6
    Admin Daniel Nenni's Avatar
    Join Date
    Aug 2010
    Location
    Silicon Valley
    Posts
    3,964
    Thumbs Up
    Received: 697
    Given: 1,990
    Quote Originally Posted by TeemuSoilamo View Post
    NVIDIA now command such power that they can get a half-node tailor-made for them? Wow.
    AI is a target market for TSMC so yes they will work closely with NVDA. You should also know that NVDA has been working closely with TSMC since the beginning of both companies 20+ years ago. In fact, Jensen Huang and Morris Chang are very close friends.

    0 Not allowed!
    Now available in print or Kindle: "Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices"

  7. #7
    Blogger Bernard Murphy's Avatar
    Join Date
    Aug 2015
    Location
    California Gold Country
    Posts
    956
    Thumbs Up
    Received: 259
    Given: 310
    Quote Originally Posted by Daniel Nenni View Post
    I just got through the NVIDIA collateral and let me say, WOW, what an incredible run they are having. The question I have is who will catch them? Certainly not AMD or Intel.

    I am wondering about the inference stuff. NVDA seems to be chasing that market with GPUs but it seems like overkill to me. FPGAs seem much more suited. I do understand the single vendor approach to AI, one vendor for both learning and inference but on a chip vs chip level FPGAs seem much better suited. Thoughts?
    Agreed on inference. The trend is to skinnying down neural nets in inference for much lower power and area - one to 4 bit multiplication and sparse-matrix handling for example. That motivates more specialized hardware/IP, potentially even on high-volume applications. FPGAs? Maybe though power remains a concern for edge nodes.

    1 Not allowed!
     

  8. #8
    Top Influencer
    Join Date
    Oct 2015
    Posts
    144
    Thumbs Up
    Received: 104
    Given: 12
    I think the training of NN is better suited to GPU. Here is a bit of a reference.

    https://www.quora.com/Why-and-how-ar...k-computations

    Most commercial and educational NN software has built in support for GPU, same can't be said for FPGA.

    Neural Networks with Parallel and GPU Computing - MATLAB & Simulink

    As I've said before, GPU commuting is ideal for algorithms that can benefit from parallelism, and inference and NNs certainly do. FPGA is highly suitable for algorithms that benefit from reprogramability, think search.

    0 Not allowed!
     

  9. #9
    Influencer
    Join Date
    Sep 2011
    Posts
    78
    Thumbs Up
    Received: 24
    Given: 2
    I was just at Eurocrypt conference. The limiting step in breaking RSA public key encryption is large matrix multiplications. Matrix multiplication is not parallizable and best for sparce matrices is n squared (number of rows times number of columns). Matrices are huge. I wonder what special hardware for sparse matrix multiplication is. Best for non sparse matrices is n**2.8.

    Also interesting is work on creating password algorithms that inherently require password breaking algorithms (exhaustive search) to require maximum memory and maximum non parallizable compute time so cracking ASICs can't be built.

    0 Not allowed!
     

  10. #10
    Blogger Bernard Murphy's Avatar
    Join Date
    Aug 2015
    Location
    California Gold Country
    Posts
    956
    Thumbs Up
    Received: 259
    Given: 310
    Quote Originally Posted by smeyer0028 View Post
    I was just at Eurocrypt conference. The limiting step in breaking RSA public key encryption is large matrix multiplications. Matrix multiplication is not parallizable and best for sparce matrices is n squared (number of rows times number of columns). Matrices are huge. I wonder what special hardware for sparse matrix multiplication is. Best for non sparse matrices is n**2.8.
    ...
    Good question. I think it would depend very much in how the matrix is sparse. I got my info from the Cadence summit on embedded neural nets (https://www.semiwiki.com/forum/conte...ural-edge.html and Embedded Neural Network Summit | Cadence IP) where sparsity is being exploited to reduce area and power over general neural algos. Here's one paper on handling spare matrices for CNNs: http://www.cv-foundation.org/openacc...CVPR_paper.pdf

    0 Not allowed!
     

Page 1 of 2 12 LastLast

Tags for this Thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •