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Thread: A more realistic take by Samsung on 7nm

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    A more realistic take on 7nm patterning by Samsung

    In this post, I briefly cover three papers from this year related to Samsung's preparation for 7nm. After reading, I found a surprisingly more realistic status than portrayed at less technical venues.

    Two of the papers are from 2017 Symposium on VLSI Technology.

    Paper T11-3 "10nm 2nd generation BEOL technology with Optimized Illumination and LELELELE" is interesting not only for its revelation of Samsung's multipatterning strategy (detailed in the "Current multi-patterning techniques" thread: but also the revelation that SADP is an emerging option for 7nm besides EUV.

    Paper T6-1 "Highly Manufacturable 7nm FinFET Technology featuring EUV lithography for Low Power and High Performance Applications" shows device data with the introduction of dual fin widths and rather few quantitative details of EUV. One interesting statement was that besides the contact layer, EUV was being applied to "minimum-pitched metal/via interconnects", the latter application being repeated several times in the paper. I take it "minimum pitch" means the minimum metal pitch (MMP) of 7nm node, so it highlights a single-pitch design restriction. It would be consistent with EUV SMO illumination favoring 36 nm pitch in recent studies. On the other hand, the other interesting statement was the comparison of EUV with DPT rather than SAQP, with the former offering >25% reduction of mask steps. This may hint that MMP is in fact larger than 36 nm.

    More detailed information on Samsung's work on EUV this year comes from their SPIE paper this year "Progress in EUV lithography toward manufacturing" (paper 1014306).

    • the pellicle's metallic layer thickness is increased in order to keep the temperature less than 400C where the pellicle is proved to be sustainable at the expense of transmittance loss.
    • In the case of NXE3300, the collector contamination rate was improved from around 1%/Bpulses to 0.5%/Bpulses by optimizing hydrogen flow and vessel temperature. NXE3350 shows similar trend just after installation, but it needs to be improved less than 0.1%/Bpulses before production starts.
    • By using 0.55NA contact hole LCDU decreases from around 3.5nm to 2.5nm due to the increase of NILS. But at 32nm pitch, which is supposedly the CH pitch for 3nm logic, LCDU increases again up to 4nm, while 2.4nm is needed in order to keep LCDU of less than 15% of half pitch.
    • After exposure of around 40,000 wafers at NXE3300, bulge defects were observed. By the highly energetic EUV photon hydrogen radicals are generated, which penetrate into the interlayer, recombine, and cause bulges.
    • Samsung developed an in-house actinic review tool using high-harmonic EUV source, zoneplate optics, and scanning microscopy called EMDRS(EUV Mask Defect Review System).

    S-S. Kim et al., "Progress in EUV lithography toward manufacturing," Proc. SPIE vol. 10143, 1014306 (c) 2017 SPIE.
    D. Ha et al., "Highly Manufacturable 7nm FinFET Technology featuring EUV lithography for Low Power and High Performance Applications," 2017 Symposium on VLSI Technology, T68 (c) 2017 JSAP, under permission of copyright holder.
    W. C. Jeong et al., "10nm 2nd generation BEOL technology with Optimized Illumination and LELELELE," 2017 Symposium on VLSI Technology, T144 (c) 2017 JSAP, under permission of copyright holder.

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    Last edited by Fred Chen; 01-14-2018 at 04:05 AM.

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