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Thread: A more realistic take by Samsung on 7nm

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    A more realistic take on 7nm patterning by Samsung

    In this post, I briefly cover three papers from this year related to Samsung's preparation for 7nm. After reading, I found a surprisingly more realistic status than portrayed at less technical venues.

    Two of the papers are from 2017 Symposium on VLSI Technology.

    Paper T11-3 "10nm 2nd generation BEOL technology with Optimized Illumination and LELELELE" is interesting not only for its revelation of Samsung's multipatterning strategy (detailed in the "Current multi-patterning techniques" thread: https://www.semiwiki.com/forum/f293/...html#post35083) but also the revelation that SADP is an emerging option for 7nm besides EUV.

    Paper T6-1 "Highly Manufacturable 7nm FinFET Technology featuring EUV lithography for Low Power and High Performance Applications" shows device data with the introduction of dual fin widths and rather few quantitative details of EUV. One interesting statement was that besides the contact layer, EUV was being applied to "minimum-pitched metal/via interconnects", the latter application being repeated several times in the paper. I take it "minimum pitch" means the minimum metal pitch (MMP) of 7nm node, so it highlights a single-pitch design restriction. It would be consistent with EUV SMO illumination favoring 36 nm pitch in recent studies. On the other hand, the other interesting statement was the comparison of EUV with DPT rather than SAQP, with the former offering >25% reduction of mask steps. This may hint that MMP is in fact larger than 36 nm.

    More detailed information on Samsung's work on EUV this year comes from their SPIE paper this year "Progress in EUV lithography toward manufacturing" (paper 1014306).

    • Pellicle metal layer is used to keep the pellicle cool enough (<400 C) but it also reduces transmission, so there is a tradeoff
    • Thru-slit CD uniformity surprisingly serious for isolated horizontal lines (compared to dense)
    • As mentioned in other presentations, collector degradation was improved to 0.5% per billion pulses but needs to drop to <0.1% per billion pulses.
    • LCDU on contact holes degrades as pitch decreases and is worse for 0.33 NA compared to 0.55 NA due to NILS being worse for the lower NA.
    • Samsung revealed a new mask defect phenomenon, called 'bulge defects', which occurred after exposing a mask for a sufficient number of wafers. The bulge is attributed to hydrogen penetration into the layers of the EUV mask.
    • Actinic (EUV wavelength) mask defect review made use of an in-house tool developed by Samsung called EMDRS (EUV Mask Defect Review System).


    References:
    S-S. Kim et al., "Progress in EUV lithography toward manufacturing," Proc. SPIE vol. 10143, 1014306 (c) 2017 SPIE.
    D. Ha et al., "Highly Manufacturable 7nm FinFET Technology featuring EUV lithography for Low Power and High Performance Applications," 2017 Symposium on VLSI Technology, T68 (c) 2017 JSAP.
    W. C. Jeong et al., "10nm 2nd generation BEOL technology with Optimized Illumination and LELELELE," 2017 Symposium on VLSI Technology, T144 (c) 2017 JSAP.

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    Last edited by Fred Chen; 1 Week Ago at 09:15 PM.
     

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