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Thread: Intel's Manufacturing Day Materials

  1. #41
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    The red triangles in the NMOS benchmark do pretty well. Unfortunately, we do not know what the red triangles represent and they are strangely absent from the PMOS chart.

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  2. #42
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    Quote Originally Posted by lefty View Post
    The red triangles in the NMOS benchmark do pretty well. Unfortunately, we do not know what the red triangles represent and they are strangely absent from the PMOS chart.
    Correct lefty, I truly believe that it was done on purpose (most likely was too good to show vs their 14++). Unfortunately I do not know what process is represented by the red triangles either. What I do know is that both 14LPP and 16FF+ are in the nmos graph, since they stated the cpps, respectively of 78 and 90nm. My educated guess is that they are 16FF+, since it would follow the same pattern of 14 and 14++ (the higher the cpp the better the xtor performance).

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    Last edited by astilo; 04-05-2017 at 09:25 AM.
     

  3. #43
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    Quote Originally Posted by Lodix View Post
    Can you post a link to the image ? It is very compressed and hard to read.

    Ruth Brain on Intel’s 14 nm Technology (PDF)

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    Last edited by Daniel Nenni; 04-05-2017 at 12:51 PM.
    Now available in print or Kindle: "Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices"

  4. #44
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    There's a very interesting analysis of Intel's manufacturing claims at Semiaccurate: Is Intel's Hyperscaling really a change? - SemiAccurate
    It's rather long winded, but the gist is
    1) "hyper scaling" is not real. Intel altered the measurement of scaling of previous nodes to make the new nodes look like they are scaling more.
    2) The charts showing reduced cost per transistor are misleading, because they assume perfect yields, but the yields are not perfect (especially for 10nm).
    3) Mid node improvements (i.e. 14nm+ and 14nm++) is presented as a new development, but it isn't because they have being doing that all along, but just kept mum about it. (Haswell was really on a 22nm+ node, just that Intel kept that detail secret.)

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    Last edited by lefty; 04-05-2017 at 01:14 PM.
     

  5. #45
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    Quote Originally Posted by lefty View Post
    There's a very interesting analysis of Intel's manufacturing claims at Semiaccurate: Is Intel's Hyperscaling really a change? - SemiAccurate
    It's rather long winded, but the gist is
    1) "hyper scaling" is not real. Intel altered the measurement of scaling of previous nodes to make the new nodes look like they are scaling more.
    2) The charts showing reduced cost per transistor are misleading, because they assume perfect yields, but the yields are not perfect (especially for 10nm).
    3) Mid node improvements (i.e. 14nm+ and 14nm++) is presented as a new development, but it isn't because they have being doing that all along, but just kept mum about it. (Haswell was really on a 22nm+ node, just that Intel kept that detail secret.)
    1) Blame the foundries with their marketing wars that removed any physical meaning from the nm in their node names. At least Intel is proposing something based not only on marketing power alone.
    2) Give me any foundry that takes into account yield in their cost per transistor graphs.
    3) This is valid remark, but at least they did not reduce the number in the node name...

    I think the main problem in the end is that the trade-offs and decision to made in the nodes is so complicated that is can't be captured in a single node number/name anymore. But this naming still demanded by marketing...

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  6. #46
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    I've been thinking about that slide showing transistor performance again. It is curious that Intel's 1st gen 14nm performs worse than the competitions 14/16nm, which are in reality a whole node behind Intel. If you compare the top boost clock of each generation of Intel's CPUs you see something quite interesting. Broadwell clocked very badly: the highest clocked SKU only reached 3.7 GHz (in fact slower than Haswell refresh). Then, when Skylake was released the clocks suddenly jumped to 4.2 GHz.
    I would say that the first iteration of 14nm was a failure, insofar as that any new node should at least perform as well as the previous node. I think Intel quickly rolled out an improved version of 14nm for Skylake, but kept that detail secret. The chart shows Broadwell as the grey dots, Skylake is not shown, but it would fall in between Broadwell and Kaby Lake (14nm++).

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  7. #47
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    Daniel, what's your insight into why Intel has cancelled the 2017 Intel Developer Forum?

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  9. #49
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    Quote Originally Posted by JeffreyHF View Post
    Daniel, what's your insight into why Intel has cancelled the 2017 Intel Developer Forum?
    It doesn't make sense to me why Intel decided to abolish (or "retire" in Intel's words) this developer forum. I don't think that's a cost issue.

    From Intel's news release:

    Intel has a number of resources available on intel.com, including a Resource and Design Center with documentation, software, and tools for designers, engineers, and developers. As always, our customers, partners, and developers should reach out to their Intel representative with questions.


    I can't stop thinking this
    self-centered
    attitude Intel has displayed. It will lead Intel into trouble.

    Another company recently got into big trouble because this kind of
    self-centered attitude is: United Airlines.


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  10. #50
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    Quote Originally Posted by JeffreyHF View Post
    Daniel, what's your insight into why Intel has cancelled the 2017 Intel Developer Forum?
    I'm okay with it. Originally it was a very technical conference but then the marketing people took over. I think they should also abolish manufacturing day. It really was ridiculous. They could have held it at the Intel HQ theater and saved thousands of dollars. They should also skip the high energy dance music, especially when introducing Mark Bohr!

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