You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!




Results 1 to 12 of 12

Thread: Intel's 10nm metal patterning contradiction - differences of hyper-NA tools?

  1. #1
    Expert
    Join Date
    Mar 2012
    Posts
    612
    Thumbs Up
    Received: 220
    Given: 195

    Intel's 10nm metal patterning contradiction - differences of hyper-NA tools?

    In this 22 nm presentation (p. 37), Intel reported 80 nm metal pitch with single patterning: https://www.intel.com/content/dam/ww...esentation.pdf

    However, in the 10nm IEDM 2017 paper, 40 nm metal pitch (20 nm half-pitch) was done by self-aligned quadruple patterning, not the expected pitch-halving double patterning.

    This is a rather unexpected, even apparently self-contradictory, choice. But the expectation is set by the assumptions.

    It might be related to the difference of available immersion tools. Some immersion tools have the maximum numerical aperture (NA) of 1.35, while others have a lower NA of 1.2. The 40 nm resolution is achievable with the 1.35 NA, achieving a k1 of (40)*(1.35)/193 = 0.28, which is just above the fundamental limit of k1=0.25. This is what was used for Intel's 22nm. On the other hand, the same 40 nm is not achievable with 1.2 NA, since k1 = (40)*(1.2)/193 < 0.25. If there are not enough 1.35 NA tools to use for Intel's 10nm, they have to reuse the 1.2 NA tools with quadruple patterning (starting from 80 nm half-pitch) instead of double patterning (starting from 40 nm half-pitch).

    Restricting to 1.2 NA tools would also increase the number of via or cut or block masks compared to 1.35 NA. Two vias or cuts 80 nm apart must use different masks on 1.2 NA but can be squeezed onto one mask with care on 1.35 NA.

    2 Not allowed!
    Last edited by Fred Chen; 07-11-2018 at 07:08 AM.
     

  2. #2
    Member
    Join Date
    Oct 2014
    Posts
    49
    Thumbs Up
    Received: 21
    Given: 1
    Why on earth could they not get a 1.35NA tool; bad planning?

    0 Not allowed!
     

  3. #3
    Admin Daniel Nenni's Avatar
    Join Date
    Aug 2010
    Location
    Silicon Valley
    Posts
    4,545
    Thumbs Up
    Received: 989
    Given: 2,489
    Quote Originally Posted by Fred Chen View Post
    In this 22 nm presentation (p. 37), Intel reported 80 nm metal pitch with single patterning: https://www.intel.com/content/dam/ww...esentation.pdf

    However, in the 10nm IEDM 2017 paper, 40 nm metal pitch (20 nm half-pitch) was done by self-aligned quadruple patterning, not the expected pitch-halving double patterning.

    This is a rather unexpected, even apparently self-contradictory, choice. But the expectation is set by the assumptions.

    It might be related to the difference of available immersion tools. Some immersion tools have the maximum numerical aperture (NA) of 1.35, while others have a lower NA of 1.2. The 40 nm resolution is achievable with the 1.35 NA, achieving a k1 of (40)*(1.35)/193 = 0.28, which is just above the fundamental limit of k1=0.25. This is what was used for Intel's 22nm. On the other hand, the same 40 nm is not achievable with 1.2 NA, since k1 = (40)*(1.2)/193 < 0.25. If there are not enough 1.35 NA tools to use for Intel's 10nm, they have to reuse the 1.2 NA tools with quadruple patterning (starting from 80 nm half-pitch) instead of double patterning (starting from 40 nm half-pitch).

    Restricting to 1.2 NA tools would also increase the number of via or cut or block masks compared to 1.35 NA. Two vias or cuts 80 nm apart must use different masks on 1.2 NA but can be squeezed onto one mask with care on 1.35 NA.
    Do you have a paper on Intel 14nm for comparison? It would be interesting to see how Intel stepped from 22nm to 14nm to 10nm?

    0 Not allowed!
    Now available in print or Kindle: "Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices"

  4. #4
    Expert
    Join Date
    Mar 2012
    Posts
    612
    Thumbs Up
    Received: 220
    Given: 195
    Quote Originally Posted by Daniel Nenni View Post
    Do you have a paper on Intel 14nm for comparison? It would be interesting to see how Intel stepped from 22nm to 14nm to 10nm?
    IEDM 2014: https://www.intel.com/content/dam/ww...esentation.pdf

    22nm: MMP=80 nm
    14nm: MMP=52 nm
    10nm: MMP=36 nm

    Note that 44 nm pitch could be ok for SADP on 1.2 NA.

    2 Not allowed!
    Last edited by Fred Chen; 07-11-2018 at 10:17 AM.
     

  5. #5
    Expert
    Join Date
    Mar 2012
    Posts
    612
    Thumbs Up
    Received: 220
    Given: 195
    Quote Originally Posted by Chipper View Post
    Why on earth could they not get a 1.35NA tool; bad planning?
    Historically, the 1.2NA tool was targeted for 45 nm node. I suppose at the time Intel was more aggressive in purchasing those tools to stay ahead at 45 nm, even though in the end not using them for 45 nm. So they may have a larger share of those tools. Still, they also purchased many 1.35NA tools as well. It's a little hard to believe the 1.35NA capacity ran out. But possibly the other players like TSMC or Samsung could have the advantage to buy relatively more 1.35NA tools, which were available shortly after 45 nm.

    0 Not allowed!
    Last edited by Fred Chen; 07-12-2018 at 12:34 PM.
     

  6. #6
    Blogger Scotten Jones's Avatar
    Join Date
    Oct 2012
    Location
    Greater Boston Area
    Posts
    604
    Thumbs Up
    Received: 270
    Given: 5
    Intel's 10nm process has a 36nm M1 pitch done with SAQP. My guess is they also use SAQP for M0 even though the pitch is 40nm to match some design rules, it likely has nothing to do with the pitch when they could clearly do SADP.

    0 Not allowed!
     

  7. #7
    Expert
    Join Date
    Mar 2012
    Posts
    612
    Thumbs Up
    Received: 220
    Given: 195
    Assuming they have enough 1.35NA tools now, would they now move M0 to SADP?

    0 Not allowed!
     

  8. #8
    Blogger Scotten Jones's Avatar
    Join Date
    Oct 2012
    Location
    Greater Boston Area
    Posts
    604
    Thumbs Up
    Received: 270
    Given: 5
    Quote Originally Posted by Fred Chen View Post
    Assuming they have enough 1.35NA tools now, would they now move M0 to SADP?
    I don't think it has anything to do with availability of 1.35NA tools, M0 and M1 are tightly coupled for routing and I think they need M0 to be SAQP for design rule reasons. I don't for a moment believe Intel doesn't have enough 1.35NA tools available. It is also possible there is something about the way it is laid out or steps heights or whatever that drives the need for SAQP.

    0 Not allowed!
     

  9. #9
    Expert
    Join Date
    Mar 2012
    Posts
    612
    Thumbs Up
    Received: 220
    Given: 195
    I'd be intrigued if there was some new consideration to use SAQP other than pitch resolution. But if the final line pitch after SAQP is 36 or 40 nm, then they could probably be using dry ArF rather than their high-end immersion tools for 144 or 160 nm pitch.

    0 Not allowed!
     

  10. #10
    Expert
    Join Date
    Mar 2012
    Posts
    612
    Thumbs Up
    Received: 220
    Given: 195
    Quote Originally Posted by Fred Chen View Post
    I'd be intrigued if there was some new consideration to use SAQP other than pitch resolution. But if the final line pitch after SAQP is 36 or 40 nm, then they could probably be using dry ArF rather than their high-end immersion tools for 144 or 160 nm pitch.
    I just looked over the IITC 2018 paper by Intel (reference below) where they described their BEOL SAQP and process. Though they did not give away all the details, if I understand the hints correctly, the M0 layout required a special process integration sequence for the line cutting arrangement, due to lots of skip-line cuts. SADP would have used thinner photoresist which probably couldn't support this process integration sequence. Just a guess.

    Reference:

    A. Yeoh et al.,"Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing," International Interconnect Technology Conference (IITC) 2018, p. 144 (c) 2018 IEEE.

    0 Not allowed!
    Last edited by Fred Chen; 08-18-2018 at 08:49 AM.
     

  11. #11
    Member
    Join Date
    Aug 2018
    Posts
    2
    Thumbs Up
    Received: 1
    Given: 0
    Quote Originally Posted by Fred Chen View Post
    I'd be intrigued if there was some new consideration to use SAQP other than pitch resolution. But if the final line pitch after SAQP is 36 or 40 nm, then they could probably be using dry ArF rather than their high-end immersion tools for 144 or 160 nm pitch.
    Hey Fred, finally got around to going through the sign up process here to give some insight. A big recent development in SAQP is three color patterning. It gives you a lot of options when it comes to pattern transfer. See EG Multi-color approach on self-aligned multiple patterning for single line cut application . Tel's been working on it quite a while. They had a great presentation at AL this year and here is one of their previous presentations as well Semiconductor scaling via self-aligned block patterning
    | SPIE Homepage: SPIE
    . I wouldn't be surprised if the etch flexibility is necessary for 10 nm.

    1 Not allowed!
     

  12. #12
    Expert
    Join Date
    Mar 2012
    Posts
    612
    Thumbs Up
    Received: 220
    Given: 195
    Quote Originally Posted by lasserith View Post
    Hey Fred, finally got around to going through the sign up process here to give some insight. A big recent development in SAQP is three color patterning. It gives you a lot of options when it comes to pattern transfer. See EG Multi-color approach on self-aligned multiple patterning for single line cut application . Tel's been working on it quite a while. They had a great presentation at AL this year and here is one of their previous presentations as well Semiconductor scaling via self-aligned block patterning
    | SPIE Homepage: SPIE
    . I wouldn't be surprised if the etch flexibility is necessary for 10 nm.
    lasserith, thanks for the information and links.

    I think it's highly likely Intel's approach was trying for something similar if not the same. In fact, they had indicated the line cuts would be orthogonal to the lines in the IITC paper.

    0 Not allowed!
     

Tags for this Thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •