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Thread: Intel 10nm process problems -- my thoughts on this subject

  1. #81
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    Quote Originally Posted by Scotten Jones View Post
    "Cobalt metallization is introduced in the pitch quartered interconnect layers in order to meet electromigration and gapfill-resistance requirements."

    I don't think gapfill-resistance is referring to electrical resistance as you appear to be assuming, I think it is referring to the difficulty of filling the narrow trenches and vias that the interconnect is fabricated in.
    Are you serious? I think it's obvious they either meant to write "electromigration, gap fill and resistance" or by writing "gapfill-resistance" referred to the tradeoff involved with the use of cobalt as cobalt gap fill is known to be problematic due to formation of voids.

    What makes you believe otherwise?

    Here is a quote from Intel's IITC paper:

    "Cobalt metallization is used in M0 and M1. Cobalt's properties provide the required excellent electromigration resistance for high performance designs. At the short-range routing distances typical of M0 and M1, the intrinsic resistance penalty of cobalt (vs. copper) is negligible, especially when the true copper volume at sub-40nm pitches is considered. Additionally, mobility of cobalt in low K dielectric is low that permits a simple titanium-based liner, thereby minimizing interlayer via resistance at these high via count layers."

    This clearly indicates Intel is using cobalt for electromigation resistance and that while the line resistance is higher, the via resistance is lower and offsets that at least to some degree consistent with the imec paper and my write up of it.
    Your writeup is concluded with a statement which is not only not found in the article, but contradicts what the abstract says. When I asked you, it turned out it was a spoken comment, but your article doesn't mention it clearly.


    Furthermore, when I asked you what that conclusion that comment was based on (sims or silicon, what circuits) you evaded the question. Do you realize that it casts very serious doubts on the credibility of that comment and, in turn, your conclusion?

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  2. #82
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    Quote Originally Posted by -AM- View Post
    No, that's not what I said at all. I said 40nm-36nm is not equal to SADP-SAQP.


    I keep bringing up Intel's 45nm process because it illustrates the trap of your assumption: you can't simply look at pitch and draw correct conclusion on that basis as to what patterning technique is used.

    Besides, we know now that Intel had to resort to quintuple and sextuple patterning for 10nm from Krzanich during his last conference call, why do you prefer not to notice it? You fall in the trap of your assumption right there.

    You can't rely on it. Relying on known pitch to draw conclusions about patterning technique is as misleading as Bohr's metric with regard to density -- it simply doesn't tell you what you really need to know, as in case of Intel it simply doesn't correspond to transistor density of their real products.
    Actually in an earlier post you said:

    "Regarding this note, 36nm vs 40nm is not the same as SADP vs SAQP. E.g. Intel went SADP on 45nm node, so for them 40nm-36nm transition would have been nothing more than 10% reduction with no changes in patterning technique."

    Clearly you are saying Intel could continue to use the same technique for 36nm as for 40nm, they can't. 10% doesn't matter, the absolute pitch matters. You can do 40nm with SADP, you can't do 36nm with SADP and while that doesn't mean you have to use SAQP, but you have to use something other than SADP and from the Intel article we know they used SAQP.

    Also Intel didn't use SADP on their 45nm node, it was LE2.

    "Besides, we know now that Intel had to resort to quintuple and sextuple patterning for 10nm from Krzanich during his last conference call, why do you prefer not to notice it? You fall in the trap of your assumption right there."

    In the Intel Q1 conference call BK said this:

    "So think of them as improvements to the various edge stuff, the lithography stuff, thin cleans and things like that in order to really drive the multi-patterning and, in some cases, multi-multi-patterning, where you have four, five, six layers of patterning to produce a feature. It's really about that. They aren't necessarily around performance."

    SAQP is a pitch quadrupling technique in one direction that uses one mask to form the mandrel for the spacers. In the orthogonal direction you have cut or block masks, sometimes a lot of them because you don't get pitch multiplication in that direction, if you have 3 or 4 or 5 cut/block masks it is still SAQP. I am not "not noticing it", I am using the generally accepted industry nomenclature. SAQP with 4 blocks masks is 5 total masks and with 5 block masks it would 6 total masks but is still SAQP.

    "Relying on known pitch to draw conclusions about patterning technique is as misleading as Bohr's metric with regard to density -- it simply doesn't tell you what you really need to know, as in case of Intel it simply doesn't correspond to transistor density of their real products."

    I actually didn't rely on the pitch to draw a conclusion on patterning technique, the patterning technique has been published.

    In terms of the "Bohr's metric" comment you can't fairly compare processes based on transistors per die area unless the designs are the same. Since that is almost never the case it is the standard industry practice to use metrics like CPP x MMP, or CPP x MMP x Tracks or the "Bohr metric" I use. I don't claim the 'Bohr metric" is perfect and I also publish SRAM cell sizes to cover Cache but the metrics are the best available.

    The whole compare transistor per die argument has been discussed on here before and this thread is already muddied enough.

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  3. #83
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    "Are you serious? I think it's obvious they either meant to write "electromigration, gap fill and resistance" or by writing "gapfill-resistance" referred to the tradeoff involved with the use of cobalt as cobalt gap fill is known to be problematic due to formation of voids.

    What makes you believe otherwise?"

    I know from other sources that Intel plates cobalt. From the original IBM copper work it is known that plating offers superior gap fill.

    " Your writeup is concluded with a statement which is not only not found in the article, but contradicts what the abstract says. When I asked you, it turned out it was a spoken comment, but your article doesn't mention it clearly. "

    I clearly state at the opening if the article that I not only read the article but also interviewed the author.

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  4. #84
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    Quote Originally Posted by -AM- View Post

    Besides, we know now that Intel had to resort to quintuple and sextuple patterning for 10nm from Krzanich during his last conference call, why do you prefer not to notice it? You fall in the trap of your assumption right there.
    This part of the Q1 2018 earnings call went like this:

    "The last part of your question about whether will it be a 10 or 10-plus-plus or 10-plus I think was your question, the yield improvements that we're making are just that, more focused on yield. So think of them as improvements to the various edge stuff, the lithography stuff, thin cleans (33:54) and things like that in order to really drive the multi-patterning and, in some cases, multi-multi-patterning, where you have four, five, six layers of patterning to produce a feature. It's really about that. They aren't necessarily around performance."

    It suggests that they attributed the yield issue to the use of multiple mask exposures on a feature layer. It is a natural consequence of SADP or SAQP to use additional masks to put breaks in the lines defined by the spacers. The breaks are necessary to define the interconnect pattern. Six does look a little excessive even with ArFi. IMEC has consistently demonstrated 3 masks for breaking the SAQP lines at a tighter pitch (32 nm).

    In any case, Intel did not "admit" to cobalt-related issues, but to patterning-related issues.

    Note: I just noticed Scotten had said pretty much the same and used the same quote, a couple of posts earlier.

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    Last edited by Fred Chen; 07-06-2018 at 04:14 PM.
     

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    Quote Originally Posted by IanD View Post
    I don't think anyone's disputing that for EUV to be used in real big-volume mass production it has to be cost-competitive with multi-patterned immersion -- hopefully cheaper, but certainly not more expensive, because lowering cost due to higher density is the only real reason to go to the next node nowadays since the power and performance improvements have slowed right down.

    If we take TSMCs latest Fab 18 planned for 5nm which will end up at around 1M wafers/year, and guess at 30 EUV mask levels (entire FEOL + all fine-pitch BEOL -- is this a reasonable guess?) this needs around 4000 wafers/hour allowing for machine availability, which probably means that just this one fab will need the entire world supply of EUV steppers...

    If anyone has better numbers I'd love to see them ;-)
    Ten NXE:3400B (7nm HVM target) tools total in 2017, 3 in Q1 2018 reported by ASML. At this rate, maybe 3 more in Q2? Most likely the plurality of these are going to Samsung.

    Doses going up would reduce the throughput of EUV tools according to a known curve. For 250 W, 20 mJ/cm2 gives 125 WPH, 50 mJ/cm2 gives about 70 WPH. The higher dose would be necessary to reduce CDU and stochastic effects.

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    Last edited by Fred Chen; 07-07-2018 at 12:57 PM.
     

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    Quote Originally Posted by Fred Chen View Post
    In any case, Intel did not "admit" to cobalt-related issues, but to patterning-related issues.

    Can patterning-related issues alone explain the abysmal performance of the Core i3-8121U? If the specifications are correct it uses significantly more power compared to 14nm parts with lower boost frequencies to boot.

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  7. #87
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    Quote Originally Posted by spartak View Post
    Can patterning-related issues alone explain the abysmal performance of the Core i3-8121U? If the specifications are correct it uses significantly more power compared to 14nm parts with lower boost frequencies to boot.
    Intel apparently did not admit anything related to parts which supposedly yielded. The patterning was in regard to process yields.

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  8. #88
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    But it's relevant to the viability of 10nm. If they solved the yield issue but performance is much worse than expected, it's not a viable process. The whole discussion is centered on both; the quad patterning issues related to yields, the cobalt plated interconnects regarding performance. The've admitted to the former, but that doesn't rule out other problems like the latter.

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  9. #89
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    Quote Originally Posted by spartak View Post
    But it's relevant to the viability of 10nm. If they solved the yield issue but performance is much worse than expected, it's not a viable process. The whole discussion is centered on both; the quad patterning issues related to yields, the cobalt plated interconnects regarding performance. The've admitted to the former, but that doesn't rule out other problems like the latter.
    The two could easily be linked; depending on whether shorts or opens are the biggest problem yield can vary with linewidth/etching tolerances, so it's quite possible that the only Core i3-8121U wafers with any yield at all are towards the slow (highest resistance) process corner, especially when using SAQP where misalignment between coloured masks could be Intel's biggest problem -- in this case the lots with thinnest metal and smallest vias will have the fewest shorts and the best (or least worst...) yield, which means slowest interconnect, and interconnect delays dominate at 7nm.

    On top of this 10nm is the first-generation process at Intel and 14nm is already on the 3rd generation of performance improvements, so we're comparing processes at very different stages of maturity. Probably by the time 10nm gets to 10++ the performance gap to 14nm will have closed up a lot, though they may have to give up some density like they did with 14nm -- assuming they *ever* get 10nm as it stands to yield enough to make the big server CPUs where most of their profit comes from...

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  10. #90
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    As I mentioned before SAQP uses two spacer widths. The second spacer width could be defining either the cobalt linewidth or the width of the dielectric between cobalt lines. The two situations are very different and represent different SAQP process integrations.

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    Quote Originally Posted by Fred Chen View Post
    Ten NXE:3400B (7nm HVM target) tools total in 2017, 3 in Q1 2018 reported by ASML. At this rate, maybe 3 more in Q2? Most likely the plurality of these are going to Samsung.

    Doses going up would reduce the throughput of EUV tools according to a known curve. For 250 W, 20 mJ/cm2 gives 125 WPH, 50 mJ/cm2 gives about 70 WPH. The higher dose would be necessary to reduce CDU and stochastic effects.
    So if we take 30mJ/cm2 (105wph?), Scott's number of 9 EUV layers, and 90% availability, TSMC's new 5nm fab at full capacity (1M wafers/year) needs about 11 EUV steppers -- which is perfectly achievable, and answers my earlier question about whether ASML supply could keep up with demand. I'm still surprised at the small number of EUV layers, I was expecting a lot more than that, but I'm not going to argue with Scott about this... ;-)

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    Last edited by IanD; 07-09-2018 at 10:03 AM.
     

  12. #92
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    Quote Originally Posted by IanD View Post
    So if we take 30mJ/cm2 (105wph?), Scott's number of 9 EUV layers, and 90% availability, TSMC's new 5nm fab at full capacity (1M wafers/year) needs about 11 EUV steppers -- which is perfectly achievable, and answers my earlier question about whether ASML supply could keep up with demand. I'm still surprised at the small number of EUV layers, I was expecting a lot more than that, but I'm not going to argue with Scott about this... ;-)
    Samsung reports close to 40 wph currently so I think it would be a very slow adoption.

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  13. #93
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    Quote Originally Posted by IanD View Post
    So if we take 30mJ/cm2 (105wph?), Scott's number of 9 EUV layers, and 90% availability, TSMC's new 5nm fab at full capacity (1M wafers/year) needs about 11 EUV steppers -- which is perfectly achievable, and answers my earlier question about whether ASML supply could keep up with demand. I'm still surprised at the small number of EUV layers, I was expecting a lot more than that, but I'm not going to argue with Scott about this... ;-)
    I was also expecting more layers of EUV but I was told that throughput is a problem for current EUV (7nm) and will need to be solved for full EUV adoption at 5nm. I would not bet on it though, EUV is a two steps forward one step back kind of thing.

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    I just wanted to say I learned a lot about SADP, SAQP and the state of 7/10nm development from this thread, even though it was a troll-dominated thread.

    Intel is not the only big chip manufacturer working with cobalt. Cobalt is apparently a very big deal for AMAT though, so it may pose competitive challenges that must be met somehow, if you’re an equipment vendor who is losing out to AMAT.

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    Quote Originally Posted by benb View Post
    I just wanted to say I learned a lot about SADP, SAQP and the state of 7/10nm development from this thread, even though it was a troll-dominated thread.

    Intel is not the only big chip manufacturer working with cobalt. Cobalt is apparently a very big deal for AMAT though, so it may pose competitive challenges that must be met somehow, if you’re an equipment vendor who is losing out to AMAT.
    Ditto for me. We are at SEMICON West this week and should have more info on Intel 10nm so stay tuned...

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    Quote Originally Posted by Daniel Nenni View Post
    Ditto for me. We are at SEMICON West this week and should have more info on Intel 10nm so stay tuned...
    Maybe some more information will surface confirming or denying the rumours that Intel's 10nm problems could kill off Nokia... (or whoever else Charlie is hinting about)

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    Quote Originally Posted by IanD View Post
    Maybe some more information will surface confirming or denying the rumours that Intel's 10nm problems could kill off Nokia... (or whoever else Charlie is hinting about)
    LOL, I don't think it could be anyone else. Only Nokia is betting on Intel 10nm and has a $20B+ Cap.

    Still waiting for Nokia to go bankrupt, nothing to sell, thousands of jobs lose, or whatever his "analysis" predict.


    Quote Originally Posted by Scotten Jones View Post
    Hi Ian

    ASML shipped 12 EUV tools last year with the 250 watt source plus several machines from 2016 are getting the 250 watt upgrade. 20 tools should ship this year and I still believe that number, 30 are due to ship in 2019 and 40 in 2020.

    Samsung has around a dozen tools with over half 250 watt sources, TSMC and Intel each have around 5 tools and GF has 2.

    I believe around 1 million wafers will get processed in 2019 with some EUV layers and around 2 million wafers in 2020.

    You can read my write up on the EUV ramp here: https://www.semiwiki.com/forum/conte...ply-chain.html


    Scott
    While those production numbers are assuring. Have they solved the downtime required for EUV, your article suggest 90% uptime. Is that the latest ASML figures or are we "expecting" 90% in time?

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    Quote Originally Posted by Daniel Nenni View Post
    Ditto for me. We are at SEMICON West this week and should have more info on Intel 10nm so stay tuned...
    Hear anything more about Intel's 10nm at SEMICON West?

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    Quote Originally Posted by Dayman58 View Post
    Hear anything more about Intel's 10nm at SEMICON West?
    Yes, I'm working on it right now.

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    I have just read the article, interesting, I am seeing other sources say 2020 for mass production, next year will be very interesting for Intel.

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