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Thread: EUV was never going to be single patterning

  1. #1
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    EUV was never going to be single patterning

    An investor presentation by ASML near the end of 2014 showed that 7nm was never going to be a single-patterning node even with EUV, but the start of a multipatterning spiral similar to what immersion is going through now. Hence, the need to develop high-NA with Zeiss. Even then, there would be no recovery to single patterning, as shown in the overlay tree below.

    From slide 49:
    https://staticwww.asml.com/doclib/in..._MvdBrink1.pdf

    EUV was never going to be single patterning-asml-euv-multipatterning-roadmap.jpg

    So, from this consideration, the throughput and corresponding source power target needs to be doubled, even without considering shot noise yet.

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    Is this REALLY the case? Suppose that EUV were reliable "enough" and cheap "enough" say in 2019 or so. Obviously the leading edge customers are at that point champing at the bit to get to EUV, whatever it costs.

    BUT there's also a whole lot of much lower volume customers stuck at 28nm or so because their volumes don't justify double patterning or worse. If TSMC, GloFo, or Samsung were to offer them 14nm with single-patterning, wouldn't that be an appealing proposition?
    Is there some reason why EUV will ALWAYS be so expensive (even after the aggressive pent-up demand of the first year or three is satisfied) that it wouldn't make sense in the sort of scenario I suggest, as just the natural successor to ArF for many (even less demanding) litho tasks?

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    Quote Originally Posted by name99 View Post
    BUT there's also a whole lot of much lower volume customers stuck at 28nm or so because their volumes don't justify double patterning or worse. If TSMC, GloFo, or Samsung were to offer them 14nm with single-patterning, wouldn't that be an appealing proposition?
    Is there some reason why EUV will ALWAYS be so expensive (even after the aggressive pent-up demand of the first year or three is satisfied) that it wouldn't make sense in the sort of scenario I suggest, as just the natural successor to ArF for many (even less demanding) litho tasks?
    EUV has many issues on its own already, to justify its use it needs to be able to demonstrate single patterning beyond that of immersion double patterning. Especially with more advanced SADP, double patterning is not something prohibitive but it has been matured, with the help of the memory industry. DRAM uses many double patterning layers, for example. As of today, immersion with double patterning is still the only way for HVM at 40-50 nm pitch. EUV is not fast or clean enough at this point. On the other hand, double patterning also forces foundries to push to the smallest pitches possible in order to reduce cost per transistor. 2 masks to achieve one-third the pitch (yes, it's possible*) is hard to beat. EUV therefore needs to show single patterning scalability below 20 nm half-pitch, which is the 7nm territory. This is where the EUV double patterning question comes in.

    *http://www.cerc.utexas.edu/utda/publications/C111.pdf see Fig. 12 wide U-bend. A similar concept is described in US Patent 7846849.

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    Layer sub-patterns with exclusive SMO

    Mixtures of different sub-pattern layouts at different locations with different optimized (pupil) sources can occur in the same layer, as expected for random logic BEOL layers with same minimum pitch. That could mean EUV needs multi-patterning due to the need for separate optimized pupils. Some recent published examples are listed below.

    The effect of multiple included layer sub-patterns in SMO was demonstrated in a paper from SPIE 2017 (W. Gillijns et al., reference below). Here the anchor pitch is 32 nm while the overlay mark is a 200 nm pitch 100 nm feature; it already took some optimization to get them together with the 2-bar in the same focus window without shifting more than 0.8 nm. However, including more sub-pattern clips from the same layer into the optimization resulted in some sub-patterns shifting up to 1 nm in the same focus window.

    More recently, ASML/IMEC/TEL showed in an SPIE Photomask 2018 paper (D. Rio et al., reference below) that SMO was more effective in addressing tip-to-tip printability with a lower illumination efficiency of the pupil (i.e., more light is discarded, due to lower pupil fill). Despite this tip-to-tip improvement, the SMO with a weighted optimization for line-space gratings and tip-to-tip gratings only did not improve printability for non-grating parts of a 32 nm pitch logic clip, e.g., where one side of the dense trench is a gap.


    References:

    J. Mulkens, J. Karssenberg, H. Wei, M. Beckers, L. Verstappen, S. Hsu, and G. Chen, "Across Scanner Platform Optimization to enable EUV Lithography at the 10-nm Logic Node," Proc. SPIE vol. 9048, 90481L (c) 2014 SPIE.

    X. Liu, R. Howell, S. Hsu, K. Yang, K. Gronlund, F. Driessen, H-Y. Liu, S. Hansen, K. van Ingen Schenau, T. Hollink, P. van Adrichem, K. Troost, J. Zimmermann, O. Schumann, C. Hennerkes, and P. Graupner, "EUV source-mask optimization for 7 nm node and beyond," Proc. SPIE vol. 9048, 90480Q (c) 2014 SPIE.

    C. Tabery, J. Ye, Y. Zou, V. Arnoux, P. Raghavan, R-H. Kim, M. Cote, L. Mattii, Y-C. Lai, and P. Hurat, "In-design and signoff lithography physical analysis for 7/5nm," Proc. SPIE vol. 10147, 1014705 (c) 2017 SPIE.

    W. Gillijns, L. E. Tan, Y. Drissi, V. Blanco, D. Trivkovic, R. H. Kim, E. Gallagher, and G. McIntyre, "Reticle enhancement techniques towards iN7 Metal2," Proc. SPIE vol. 10143, 1014314 (c) 2017 SPIE.

    D. Rio, V. Blanco, J.-H. Franke, W. Gillijns, M. Dusa, E. De Poortere, P. Van Adrichem, K. Lyakhova, C. Spence, E. Hendrickx, S. Biesmans, K. Nafus, "EUV pupil optimizations for 32nm pitch logic structures," Proc. SPIE vol. 10809, 108090N (c) 2018 SPIE.

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    Through-slit SMO (LithoVision 2017)

    An interesting update at LithoVision 2017 by Mentor Graphics (Director Dr. John Sturtevant), among other interesting things, referred to variation of aberrations (indicated by Zernike coefficients) across tools and across slit positions. Such aberrations require SMO (source-mask optimization) corrections, per tool, per slit position (essentially multiple patterning by one mask per corrected slit position).

    Mentor Graphics Director Details Challenges for Edge Placement Control in 2020

    This in fact could have been anticipated years ago: Modeling and experiments of non-telecentric thick mask effects for EUV lithography | Chiew-Seng Koay and Greg McIntyre - Academia.edu and cross-slit aberration variations in EUV tools are generally acknowledged now.

    NXE 3400 aberrations are still comparable to older NXE 3350 models: http://pfwww.kek.jp/PEARL/EUV-FEL_Wo.../01_Lercel.pdf (slide 9) The thermal aspects have not even been considered yet.

    At different slit positions, there would be different 3D shadowings of the same feature thick mask patterns. Thus, the SMO would need to be correspondingly different at different slit positions.

    The different slit position exposures also would need to be stitched together.

    Background details: An aberration is a deviation of the wavefront from the target, in other words, the illumination direction is off. This will impact the depth of focus (for k1<0.5), unless the pitch is retargeted. OPC involving feature resizing or repositioning does not affect this. But it is not tolerable for design for the minimum metal pitch to vary from 36 to 42 nm at different slit positions, differently for each EUV tool. So the illumination must be varied for different slit positions, different for each EUV tool. On each tool, the stitching of multiple mask exposures should be expected.

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    An SPIE 2018 paper from Mentor Graphics indicated that with SMO application to the 24-36 nm pitch metal layers, it was preferred to use EUV as a second exposure for cutting rather than as a single standalone exposure. A part of this is the pattern diffraction itself independent of EUV, but 3D mask effects are EUV-specific.

    Reference:

    R. K. Ali, A. H. Fatehy, N. Lafferty, and J. Word, "Ultimate patterning limits for EUV at 5nm node and beyond," Proc. SPIE vol. 10583, 1058321 (c) 2018 SPIE.

    https://www.spiedigitallibrary.org/p...f3Vqblm_Yq9-8K

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