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Thread: Brief summary/comparison of TSMC and Samsung EUV 7nm processes

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    Brief summary/comparison of TSMC and Samsung EUV 7nm processes

    TSMC (N7+): https://www.eetimes.com/document.asp?doc_id=1333827
    - 1.2X density compared to N7
    - up to 12% power reduction compared to N7
    - up to 4 EUV layers
    - tracks assumed the same

    => N7 MMP=40 nm, assuming 10% reduction each direction gives 36 nm for N7+.

    Samsung (7LPP): Samsung Electronics Starts Production of EUV-based 7nm LPP Process – Samsung Global Newsroom
    - 1.4x density ("area efficiency") compared to 10nm
    - up to 50% power reduction compared to 10nm
    - 20% fewer masks compared to non-EUV
    - 6.75 tracks compared to 8.75 tracks 10nm (https://www.semiwiki.com/forum/conte...7nm-vlsit.html)

    => With 10nm MMP=48 nm, 1.4/(8.75/6.75) ~1.08x increase in pitch density means MMP for 7LPP is hardly changed (46 nm).

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    Last edited by Fred Chen; 4 Weeks Ago at 01:50 PM.
     

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    Quote Originally Posted by Fred Chen View Post
    TSMC (N7+): https://www.eetimes.com/document.asp?doc_id=1333827
    - 1.2X density compared to N7
    - up to 12% power reduction compared to N7
    - up to 4 EUV layers
    - tracks assumed the same

    => N7 MMP=40 nm, assuming 10% reduction each direction gives 36 nm for N7+.

    Samsung (7LPP): Samsung Electronics Starts Production of EUV-based 7nm LPP Process – Samsung Global Newsroom
    - 1.4x density ("area efficiency") compared to 10nm
    - up to 50% power reduction compared to 10nm
    - 20% fewer masks compared to non-EUV
    - 6.75 tracks compared to 8.75 tracks 10nm (https://www.semiwiki.com/forum/conte...7nm-vlsit.html)

    => With 10nm MMP=48 nm, 1.4/(8.75/6.75) ~1.08x increase in pitch density means MMP for 7LPP is hardly changed (46 nm).
    I don't know about Samsung but your assumptions are wrong for TSMC N7+ (which has 5 EUV layers). The only metal which changes pitch with EUV is metal 1, this reduces from 57nm (matches CPP) to 38nm (3 M1 per 2 CPP). N7+ density increase comes from better M1 routing and SDB(CPODE) cell libraries, power decrease comes from this (smaller area = shorter tracks = lower capacitance) and also ("up to...") addition of 1-fin libraries (lower capacitance and leakage) for non-critical paths.

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    Quote Originally Posted by IanD View Post
    I don't know about Samsung but your assumptions are wrong for TSMC N7+ (which has 5 EUV layers). The only metal which changes pitch with EUV is metal 1, this reduces from 57nm (matches CPP) to 38nm (3 M1 per 2 CPP). N7+ density increase comes from better M1 routing and SDB(CPODE) cell libraries, power decrease comes from this (smaller area = shorter tracks = lower capacitance) and also ("up to...") addition of 1-fin libraries (lower capacitance and leakage) for non-critical paths.
    Ok thanks for your information. I got the 4 layers by quoting from the EETimes source. It did strike me as a little off (5 made more sense for M0-M4 for example). Also, I thought M1 was allowed to be as low as 40 nm.

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    Quote Originally Posted by Fred Chen View Post
    Ok thanks for your information. I got the 4 layers by quoting from the EETimes source. It did strike me as a little off (5 made more sense for M0-M4 for example). Also, I thought M1 was allowed to be as low as 40 nm.
    The EUV layers are mainly contacts/vias/MEOL because of current lack of usable pellicles, I expect this is same for Samsung. M1 is 54nm minimum pitch in the rules but in practice has to match CPP which is 57nm.

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    Quote Originally Posted by IanD View Post
    The EUV layers are mainly contacts/vias/MEOL because of current lack of usable pellicles, I expect this is same for Samsung. M1 is 54nm minimum pitch in the rules but in practice has to match CPP which is 57nm.
    From their 8LPP publication, Samsung indicated they were going to LEx4 for their metal layers. I'd be surprised if they didn't target these layers for EUV.

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    Quote Originally Posted by Fred Chen View Post
    From their 8LPP publication, Samsung indicated they were going to LEx4 for their metal layers. I'd be surprised if they didn't target these layers for EUV.
    Quote from https://www.eetimes.com/document.asp?doc_id=1333881

    "Both Samsung and TSMC will apply EUV probably only to two chip layers at 7nm, so far not using protective pellicles that are still in development, said Handel Jones, president of International Business Strategies. They will extend EUV to perhaps six layers at 5nm nodes, but that may not come until 2021, when pellicles will have sufficient durability and light-transmission capabilities."

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    Last edited by IanD; 3 Weeks Ago at 02:45 AM.
     

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