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Thread: Is it worth digging deeper in asynchronous?

  1. #21
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    It is not that a '1' bit has any energy, rather that it takes a flow of current through a conductor on the chip to change the voltage of the wire. That current flows also through a transistor. Both have resistance and current flowing through a resistor generates heat, duh! Then adding a second wire that changes to a '1' from a '0' doubles the heat, OMG!

    Clock distribution does generate considerable heat and as I mentioned before the wiring delay ratio to switching speed probably makes async possible. P&R/placement/STA modification along with an event driven simulator are needed although I don't see the need for continuous event timing that was mentioned before.

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  2. #22
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    ASYNC featuring low power long battery life ROW solar "smartphone"

    Thanks for any help. Request your input. Developing OPEN (free to anyone) Tech Spec for M-KOPA ASYNC featuring low power long battery life ROW, 7B ppl TAM, inexpensive smartphone, and a less expensive W3C RTC version, i.e. without cellular.
    Any ball park cost figure? 28M$? at 28nm? Currently - "...
    M-KOPA has also sold over 9,000 Huawei and Samsung smartphones in the $50 to $100 price range. It is now shifting over 1,000 smartphones per month..." If it's possible with ASYNC to get 10X (or more?) battery life at the same price .... that would be good. Noob to semiwik ... so hope this is ok topic. For "product spec" need both the tech ASYNC knowledge and the cost knowledge ... (also posted on cost/transistor thread I saw recently )
    8/18/2016 article sweet spot cost/transistor ...
    "... At 5nm, it will cost $500 million or more to design a “reasonably complex SoC,” Johnson said. In comparison, it will cost $271 million to design a 7nm SoC, which is about 9 times the cost for a 28nm planar device, according to Gartner...."

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  3. #23
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    Art,
    I have no proof but it seems Philips Xenium phones are async inside. My old Xenium X1560 (not smartphone) requires charging every 2-3 weeks. The same refers to every Xenium phone (even for smartphones) - just look into their specs.

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  4. #24
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    Power Management in theAmulet Microprocessors circa 2001

    Amulet2e "power-efficiency of 280 MIPS/W" ...
    I'd like to know/work out/calculate power-efficiency for an updated ASYNC ARM design ...
    Call is Amulet28 in honor of the early work, and 28 for the sweet spot in cost/transistor fab today ...

    Classic ...
    " ... Amulet2e, shown in Figure 6, has been fabricatedand successfully runs standard ARMcode. It was produced on a 0.5-µm, three-metallayerprocess. It uses 454,000 transistors (93,000of which are in the processor core) on a diethat is 6.4 mm square. In the fastest availableconfiguration, the device delivers 42 Dhrystone2.1 MIPS (million instructions per second) witha power consumption of about 150 mW in thecore logic—which includes the processor coreand cache memory, but excludes the I/Opads—running at 3.3 V. This is faster than theolder ARM 710 but slower than the ARM 810,which was fabricated at about the same time.It represents a power-efficiency of 280 MIPS/W,which is as good as either of the clocked CPUs. ..."

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  5. #25
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    @Art Scott: Somehow I missed the notification of your reply, just came across it.

    Before Verilog hardware design was called logic design because nets were defined using Boolean Algebra. which is the only good way.

    Apparently it was assumed that simulation to create waveforms was adequate for verification, and on and on...

    Digital hardware is quite simple as there are gates, flip-flops, and pins. (registers and memories are equivalent to arrays of flip-flops)

    The essence of design is define the functional sequences to produce meaningful outputs determined by sequences of inputs.

    Of course you already know this. The two other necessary thing is events that occur when inputs change or internal states change.

    The time for nets to resolve is critical and rather than using a clock period that is long enough for the longest path to resolve, a delay time can be
    generated that is matched to the path delay for the currently active path. The delay is triggered when the change is enabled, but the change occurs at the end of the delay.

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