You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!




Page 2 of 3 FirstFirst 123 LastLast
Results 11 to 20 of 25

Thread: Is it worth digging deeper in asynchronous?

  1. #11
    Member
    Join Date
    Nov 2015
    Location
    Russian Federation
    Posts
    12
    Thumbs Up
    Received: 6
    Given: 7
    Staf,
    My boss allows me to use our tools for my experiments. But i am afraid you are right: make the chip on the fab is a little different from just using tools for experiments. It will be complicated to convince our CEO to allow me produce test chip under our licenses, but not impossible.

    pmat,
    Thank you for the advice. I knew about ASYNC, and i had read many of their papers.
    Concerning my approach to async design, I studied all popular approaches. For my opinion, BD approach (like in HS or MIT chips) is truly a bit complicated for a regular designer; NCL approach is proprietary, heavyweight, and badly synthesizable. So i chose the classical self-timed approach (also known as NCL_X) with completion detectors. And finally, I gained success in adopting this schemes for the standard synchronous flow (RTL to GDS). The flow consists of the traditional steps: synthesis, place and route, with one exception: it requires the intermediate synchronous netlist translation into dual rail after the synthesis. Netlist translation is provided by the Perl script using Verilog-Perl library. The clock network is replaced by the GALA sub-circuit based on Muller's C-elements (similar to Sutherland's control circuit). The disadvantages of dual-rail four-phases approach are well known: low speed (due to completion detection sub-schemes) and a high consumption (due to high switching activity of signals). But, it is fully delay insensitive (with some restrictions to P&R). The question is - where these schemes may be applied: slow and with high consumption, but very robust to delay variations. IoT, probably. I don't sure.

    simguru,
    Thank you for ideas.
    I also use AMS, but it is too hard to model schemes larger than ~10k transistors and nearly impossible to model schemes with more than 100k cells. So i prefer to use the verilog netlist simulation with SDF. I had no problems with models because my approach exploits only RS-latches and C-elements, which have quite a simple Liberty description.

    1 Not allowed!
     

  2. #12
    Expert
    Join Date
    Nov 2010
    Location
    Silicon Valley USA
    Posts
    937
    Thumbs Up
    Received: 142
    Given: 96
    Quote Originally Posted by Torq View Post
    Staf,
    ...

    simguru,
    Thank you for ideas.
    I also use AMS, but it is too hard to model schemes larger than ~10k transistors and nearly impossible to model schemes with more than 100k cells. So i prefer to use the verilog netlist simulation with SDF. I had no problems with models because my approach exploits only RS-latches and C-elements, which have quite a simple Liberty description.
    I have a book on asynchronous design, so I know what a C-element looks like

    I mentioned Xyce because it's a parallel processing simulator designed for higher capacity. You don't really want to simulate at transistor level, which is why it's good to be able to do behavioral analog models (which don't need solver support). Digging back into the neural-network (NN) stuff there are ways to auto-generate block-level behavioral models using NNs that will probably do the job nicely (for FDSOI/DVFS too). IoT/AMS is also a driver for this.

    You could talk to eFabless about Xyce and making experimental chips.

    1 Not allowed!
     

  3. #13
    Expert
    Join Date
    Jan 2011
    Location
    The land of beer and chocolate
    Posts
    933
    Thumbs Up
    Received: 245
    Given: 319
    Quote Originally Posted by Torq View Post
    Staf,
    My boss allows me to use our tools for my experiments. But i am afraid you are right: make the chip on the fab is a little different from just using tools for experiments. It will be complicated to convince our CEO to allow me produce test chip under our licenses, but not impossible.
    Good to know you are aware. Microelectronics industry is a relatively small industry and from experience we know EDA vendors will ask questions on products where origin or flow is not clear.

    Quote Originally Posted by Torq View Post
    The disadvantages of dual-rail four-phases approach are well known: low speed (due to completion detection sub-schemes) and a high consumption (due to high switching activity of signals). But, it is fully delay insensitive (with some restrictions to P&R). The question is - where these schemes may be applied: slow and with high consumption, but very robust to delay variations. IoT, probably. I don't sure.
    I think you answered yourself the question why asynchronous is not used more; the power in PPA is getting more and more important.
    Even for sensors in IoT I think most of them want to process data coming from the sensor and before sending it to the Internet. That will involve some more intensive datapath logic and you want that with as low power consumption as possible. Sometimes asynchronous is sold as being able to avoid the clock tree power consumption but by your used technique that seems to be undone by the higher datapath power consumption. Additionally area is directly related to cost per chip if chip is not pad limited. Cost is again very important in the lower margin IoT world; earning 30 or 40 cents on a chip is a difference of 25%.
    Also I think the cases where delay insensitivity is the requirement are small; most of the time one wants to know how fast something will perform.

    1 Not allowed!
    Last edited by Staf_Verhaegen; 11-04-2016 at 05:39 AM.
    Trust me ...
    I know what I am doing.

  4. #14
    Member
    Join Date
    Nov 2011
    Posts
    6
    Thumbs Up
    Received: 1
    Given: 3
    simguru, why are you saying that EDA companies have not introduced asynchronous design methodologies instead of RTL ? Please refer to "Communicating Process Architectures 2005 : Handshake Technology". HS had a complete asynchronous methodology to create asynchronous circuits.

    0 Not allowed!
     

  5. #15
    Member
    Join Date
    Nov 2011
    Posts
    6
    Thumbs Up
    Received: 1
    Given: 3
    torq, NCL_X is not fully delay insensitive. How do you cope with signal orphans between reset/set phases? Achieving fully delay "insensitiveness" is far more complicated.

    I agree with the rest of your comments about the cost of the dual rail circuits.

    0 Not allowed!
    Last edited by pmat; 11-04-2016 at 06:03 AM.
     

  6. #16
    Member
    Join Date
    Nov 2015
    Location
    Russian Federation
    Posts
    12
    Thumbs Up
    Received: 6
    Given: 7
    Staf,
    This is a tricky question about consumption, because asynchronous circuits operate easily under a threshold voltage where synchronous are inoperable. But you are right about the cost - dual rail encoding takes at least twice as much area (3-5x actually, depends on completion detection sub-scheme). I have never thought about it, thank you!

    pmat,
    There are two major approaches to completion detection in Dual Rail: you may put detection on elements outputs (QDI), or - you may put it on every input (DI). The second approach is a lot harder, but eliminates the problem of wire-orphans for ever. The first approach may be considered as a DI too with some restrictions to P&R: you should take care about so-called isochronous forks.

    Ok, thank you guys! It seems, it is better for me to abandon this.

    1 Not allowed!
    Last edited by Torq; 11-05-2016 at 12:37 PM.
     

  7. #17
    Expert
    Join Date
    Nov 2010
    Location
    Silicon Valley USA
    Posts
    937
    Thumbs Up
    Received: 142
    Given: 96
    Quote Originally Posted by pmat View Post
    simguru, why are you saying that EDA companies have not introduced asynchronous design methodologies instead of RTL ? Please refer to "Communicating Process Architectures 2005 : Handshake Technology". HS had a complete asynchronous methodology to create asynchronous circuits.
    Simulating asynchronous circuits requires continuous time simulation (and a PWL modeling style) that Verilog doesn't support.

    Verilog-AMS can do it, but the available implentations are not designed for digital work.

    Silistix tried to do async. NoC synthesis, but the routing tools are tuned up for synchronous and do the wrong thing.

    0 Not allowed!
     

  8. #18
    Member
    Join Date
    Nov 2011
    Posts
    23
    Thumbs Up
    Received: 5
    Given: 0
    Generation of timing delays to allow nets to resolve has been a major problem, but Intel/Altera Stratix 10 has put "registers everywhere" in the fabric and are choosing the one to use based on timing during P&R. The next step would be to generate a wiring delay equal to net delay to clock the registers rather than placing the register based on path delay.

    Conceptually it would be a tapped delay line with timing determined by the data path pipeline.

    Some years ago one of IBM's mainframes used wire jumpers to generate delays of 1.2 ns per foot(or something like that)

    How to get their attention???

    1 Not allowed!
    Last edited by Karl S; 11-05-2016 at 10:52 AM.
     

  9. #19
    Member
    Join Date
    Nov 2016
    Posts
    5
    Thumbs Up
    Received: 1
    Given: 12
    Q:
    1A) is there any future for the the async?
    Yes! The future is now.
    The Landauer limit LAW too HOT too much power too small event has occurred for synchronous design.
    ASYNC is the answer to the end of Moore's law (lore).
    Pivot or perish. Businesses must accrue the benefits of ASYNC. Existing semi tech using ASYNC can realize great value.
    And avoid disastrous very expensive business threatening HOT flaming device events.

    This semiwiki post "About That Landauer Limit… by Bernard Murphy" is good -

    U.S. Convenes Chip Study Group White House explores China, Moore’s law

    Erik Demaine. “So we need to develop a new way to think about computation.” He and his colleagues in the MIT Computer Science and Artificial Intelligence Laboratory have been doing just that.



    1B) Do any big companies provide R&D in the async field?
    Not as many do that should. See "Chip Study Group" list. Some have a hammer so the world is a nail to them.
    Also check out sponsors of - 23rd IEEE International Symposium on Asynchronous Circuits and SystemsMay 21-24 2017, San Diego, California, US
    2016 had Intel and nVidia among others.

    Please consider getting involved, contributing - ASYNC 2017 Call For Papers -
    They are open to Fresh Ideas - - ASYNC 2017 will accommodate a special workshop to present “fresh ideas” in asynchronous design, that are not yet ready for publication. We solicit 1-to-2-page submissions for the workshop, which will go through a separate light-weight review process. Accepted submissions will be handed out at the workshop.

    In summary ... ASYNC now!

    1 Not allowed!
     

  10. #20
    Member
    Join Date
    Nov 2016
    Posts
    5
    Thumbs Up
    Received: 1
    Given: 12

    Timely ...
    Low Power VLSI Circuit Design using Energy Recovery Techniques

    V. S. Kanchana Bhaaskaran (VIT University, India)

    Source Title: Design and Modeling of Low Power VLSI Systems
    Copyright: © 2016 |Pages: 37

    DOI: 10.4018/978-1-5225-0190-9.ch006

    0 Not allowed!
     

Page 2 of 3 FirstFirst 123 LastLast

Tags for this Thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •