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Thread: TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM

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    TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM

    Kevin Gibb
    Product Line Manager, Process


    TechInsights has been on the hunt for some time now for Samsung’s 20 nm DDR4 DRAM, and we have finally found them populated on a 32 GB registered dual in-line memory module (RDIMM). The module is populated on both sides with 36 K4A8G045WB 8 Gb DDR4 DRAM chips.

    TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM-figure-1.jpg
    Figure 1: Samsung 32 GB 20 nm DDR4 Memory Module

    Each of the DRAM packages contains a single 5.8 mm x 9.7 mm large die as seen in Figure 2. Our curiosity is peaked by the small pads seen adjacent each bond pad. These are just visible in Figure 2, but are readily seen in the enlarged image, Figure 3.

    TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM-figure-2.jpg
    Figure 2: Samsung 20 nm DDR4 Die Photograph

    Samsung’s product literature for its 32 GB RDIMM makes reference to future capacity expansion to 128 GB using 3D through silicon vias (TSV) to stack the 8 Gb dies one on top of the other. The dies will likely be bumped together with a bump structure to these small TSV bond pads shown in Figure 3, and through silicon vias will be used to enable die stacking.

    TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM-firgure-3.jpg
    Figure 3: TSV Bond Pads

    Figure 4 is a SEM cross section through one of the TSV bond pads. The pad is about 30 µm in diameter and a 14 µm central area is free of polysilicide structures on the surface of the silicon substrate. The area outside this central region is patterned with STI and polycide and these may be used to relieve stresses that accompany the TSVs. The TSVs themselves, when implemented, will almost certainly to be less than 14 µm in diameter, possibly as small as 8 µm. The mismatch in thermal expansion coefficients between the TSV fill material (Cu or W) and the silicon die and dielectric layers has been a cause for reliability concerns for some time. Samsung has placed a large number of tall W vias just outside the right edge of the TSV pad area. There are considerably more of them just outside the view of Figure 4 suggesting that they are being used to add mechanical strength to the dielectric stack.

    TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM-figure-4.jpg
    Figure 4: TSV Landing Pads in Cross Section

    Figure 5 is an enlarged view of the left side of the TSV region. A copper metal 2 plate will likely be the land for the TSV that will be laser drilled from the backside of the die in a via last process. This copper pad is connected by tungsten filled vias to the overlying aluminum TSV bond pad. A patterned metal 3 lies between metal 2 and metal 4 that are likely being used for stress relief.

    TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM-figure-5.jpg
    Figure 5: Edge of TSV Region


    This DDR4 is now in our labs for analysis and we will be publishing a structural analysis report on the device in the near future. In the meantime, we are on the hunt for the 128 GB RDIMM with the stacked dies.

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    TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM

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    This is pretty amazing, the first TSV I've encountered. And its in DRAM, the most cost-conscious level of the semiconductor industry. Now that it's happened, it kind of makes sense to me--combining two known good parts and experiencing a yield loss due to a fragile TSV probably works in the practical world only when the two parts are cheap. Is there a way to rework the TSV if it fails, I wonder?

    32GB on a DIMM isn't a bad achievement in itself. What's the voltage for this?

    If Samsung is using this with DRAM, how long can it be until they are making packages of DRAM, NAND and possibly applications processors? This could enable some really, really amazing new mobile devices.

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    Last edited by benb; 03-29-2015 at 10:17 AM.
     

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    Kevin,

    Thanks for the details from TechInsights on the Samsung 20 nm RAM chips.

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    Daniel Payne, EDA Consultant
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  4. #4
    msporer
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    Quote Originally Posted by benb View Post
    This is pretty amazing, the first TSV I've encountered. And its in DRAM, the most cost-conscious level of the semiconductor industry. Now that it's happened, it kind of makes sense to me--combining two known good parts and experiencing a yield loss due to a fragile TSV probably works in the practical world only when the two parts are cheap. Is there a way to rework the TSV if it fails, I wonder?

    If Samsung is using this with DRAM, how long can it be until they are making packages of DRAM, NAND and possibly applications processors? This could enable some really, really amazing new mobile devices.
    TSVs have been used in image sensors for a long time. Aptina comes to mind. And there is this: https://youtu.be/43ljcHtRaD8

    You hit the nail on the head when you identified the cost of the DRAM as the reason why it can be successful. The cost of yield loss is manageable for a DRAM.

    TSVs cannot be reworked, but stacks can implement redundant and remappable TSVs.

    The biggest challenge will be mapping the TSV array from one die to the next. JEDEC addresses this for future TSV based memories.

    NAND does not have the same bandwidth potential of a DRAM so for now is not using using TSVs despite already stacking 8H and 16H in a package.

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