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Thread: Recent paper on alternatives to the 7-nm node, and possibility of a simpler means.

  1. #1
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    Recent paper on alternatives to the 7-nm node, and possibility of a simpler means.

    A recent paper described new methods for obtaining greater performance without going to the challenging 7-nm node [1]. However, improved metrology at the 7-nm and finer nodes may be a quicker and more efficient approach. Carrier profiling is required to test the nano-scale operation of a device in fault localization and failure analysis. The two tools used now for carrier profiling at the 7-nm node are Scanning Spreading Resistance Microscopy (SSRM) with a resolution of 20 nm and Scanning Capacitance Microscopy (SCM) with a resolution of 10 nm. These limits are shown in papers by IMEC [2] and the inventor of SCM [3]. At the 7-nm node, wouldn't it be more reasonable to require a resolution of 0.7 nm (10% of the node dimension)? Our group is developing a new technology which shows promise for achieving true sub-nm resolution with nondestructive measurements [4]

    [1] S.K. Moore, "3 Directions for Moore's Law", IEEE Spectrum, Nov. 2018.
    [2] T. Hantschel, et al., Microelectron. Eng. 159 (2016) 46-50--See Fig. 1, contradicting "sub-nm" in the title.
    [3] E. Bussmann and C.C. Williams, Rev. Sci. Instrum. 75 (2004) 422-425.
    [4] M.J. Hagmann, Microscopy & Microanalysis-2018, post-deadline poster PDP-18.

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    Can you tell more on this? Is there a PDF for it or link?

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    KingSeGa:
    Brief summary: By focusing a low-power mode-locked laser on the tunneling junction of a scanning tunneling microscope hundreds of microwave harmonics at integer multiples of the laser pulse repetition frequency are superimposed on the tunneling current. Each harmonic, is at attowatt power level but has a signal-to-noise ration exceeding 20-dB because each harmonic sets the present state of the art for a narrow-linewidth microwave source (Q greater than 10^10). The harmonics are generated by optical rectification of the laser radiation so they are present without having a DC tunneling current. Each harmonic has maximum power at a tip-sample distance such that the tunneling resistance is equal to the spreading resistance in the sample electrode. Thus, we use the harmonics as the basis for feedback control of the tip-sample distance instead of using the DC tunneling current, so that there is no need for a DC bias voltage or a DC tunneling current. For measurements made under the same conditions with samples having different resistivity, the measured attenuation of each harmonic, which is caused by the spreading resistance, may be used to determine the sample resistivity--and thus, the carrier density. The sub-nm resolution in the measurement corresponds to the radial extent of the spreading resistance. Our first measurements with semiconductors are described in [5]. I have also provided a title and DOI for reference [4] which is available on Research Gate.

    [5] C. Rhoades, J. Rasmussen, P.H. Bowles, M.J. Hagmann, and D.A. Yarotski, DOI: 10.1109/WMED.2016.7458278, ISBN: 978-1-4673-8399-8.
    [4] M.J. Hagmann, "New method in Scanning Probe Microscopy-potentially higher stability and finer resolution", Microscopy & Microanalysis-2018, post-deadline poster PDP-18. DOI: 10.13140/RG.2.2.34585.72804.2804.




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    Saturday, when I posted this message, I was aware of the announcement that advanced cell phones based on 7-nm devices may be released within 6 months. However today, at a local Apple Store, I saw the iPhone XS, XS Max, and XR which are based on the 7-nm chip with 6.9 billion transistors. I learned that Apple released the XS and XS Max on Sept. 21st, and the XR on Oct. 26th. Thus, the progress to finer lithography nodes is faster than I had realized. As I previously mentioned, DARPA funding has been used to develop two new methods to obtain greater performance without requiring the 7-nm and finer nodes [1]. I would suggest that it is reasonable to test if the relatively simple technology that we are developing [4] to correct for the present deficiency in metrology [2],[3] is sufficient before taking the option of replacing the present facilities and methods for production to enable the two new methods.

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    Hi, If you found that progress is faster than you previously realized, you might be interested in further reading on this topic.

    Let me move to our N5 status. Our N5 technology development is on schedule. We have completed the design solution development and are ready for customers' design start. The N5 risk production schedule in first half 2019 stays the same. Compared to N7, TSMC's N5 deliver 1.8x to 1.86x logic area reduction and close to 15% to 18% speed gain and ARM A72 core. We expect to receive first customer product tape-out in spring of 2019, followed by production ramp in first half 2020.

    Apple will use 5nm in 2020 so you can bet it will be in HVM in the first half of 2020. From what I hear 5nm test chips are meeting/exceeding expectations and the PDK is solid so I see no reason to doubt TSMC’s 5nm schedule at this time.
    https://www.semiwiki.com/forum/conte...cussion-e.html

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    One other way to pick up speed is through advanced materials and their creative use. There are a number of processes and materials on the horizon.

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  7. #7
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    Arthur: I agree that advanced materials offer possibilities but, regardless of what materials you are using and whether or not you use Extreme Ultraviolet Lithography or other means for fabrication, the problem is that you cannot "see" what you have made. As I mentioned in my seed for this thread the publications by those producing SSRM and SCM instruments for carrier profiling show the resolution is no finer than 20-nm and 10-nm, respectively. These are the only two methods being used for carrier profiling--even at the 7-nm node. This is like trying to manufacture cars using a wooden ruler for metrology. Electronic tests are used to verify that the devices are functioning properly and point to probable locations for the faults but then the resolution in SSRM and SCM is not sufficient to determine the fault and how it may be corrected. I have heard that the failure rates are as high as 80% at the finer nodes.
    As a quick question to those of you who are more familiar with the business aspects: I have no reason to believe that TSMC has better instrumentation than GF, so is it reasonable that TSMC may be "eating" an unusually high failure rate at 7-nm until GF and the others offer no competition in the 7-nm market? TSMC has already done risk production at the 5-nm node.

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