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Thread: Qualcomm commits to TSMC 7nm

  1. #31
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    Samsung is moving to mid-teen (1y) nm DRAM to keep ahead of the others, without EUV. That also happens to be about where the EUV tools lose their practical resolution.

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  2. #32
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    Quote Originally Posted by Fred Chen View Post
    Samsung is moving to mid-teen (1y) nm DRAM to keep ahead of the others, without EUV. That also happens to be about where the EUV tools lose their practical resolution.
    Attention, the naming game is true also in DRAM, in 1y there is nothing at 10nm, no more than there is anything that is 7nm in TSMC/Intel/Samsung. And there is also the market of 3D NAND (today stuck at 40-60nm pitches). In both the pitch and image fidelity (i.e. process window) would still benefit from EUV if it becomes suitable for production.
    And ASML/Zeiss have started looking into 0.55 NA for EUV that would extend the resolution.

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  3. #33
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    Quote Originally Posted by SPQR54 View Post
    Attention, the naming game is true also in DRAM, in 1y there is nothing at 10nm, no more than there is anything that is 7nm in TSMC/Intel/Samsung. And there is also the market of 3D NAND (today stuck at 40-60nm pitches). In both the pitch and image fidelity (i.e. process window) would still benefit from EUV if it becomes suitable for production.
    And ASML/Zeiss have started looking into 0.55 NA for EUV that would extend the resolution.
    The DRAM cell dimensions are not so easy to escape scrutiny. TechInsights regularly reverse engineers leading edge products. Samsung previously showed 18 nm half-pitch in the active silicon cell area. Micron and SK Hynix are following closely, so I would guess Samsung 1y is about 16 nm. The NXE:3400 tool feature details were disclosed last year, it is not good at direct exposure at this resolution, showing in tip gap difficulties. So SAQP cannot be avoided. But the other concern is the finer cutting still requires higher EUV doses, due to photon shot noise. 1y shouldn't require extra cutting compared to 18 nm on currently used tools.

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  4. #34
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    I see your point Fred, but assuming EUV is up for real production wouldn't you prefer double EUV exposure to quadruple exposure with immersion? Even if in memory mask cost is negligible, the reduction in number of process steps can still be important. I am also interested in your opinion of EUV impact in NAND.
    (confession to make, I am not very good at DRAM ...)

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  5. #35
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    Quote Originally Posted by SPQR54 View Post
    I see your point Fred, but assuming EUV is up for real production wouldn't you prefer double EUV exposure to quadruple exposure with immersion? Even if in memory mask cost is negligible, the reduction in number of process steps can still be important. I am also interested in your opinion of EUV impact in NAND.
    (confession to make, I am not very good at DRAM ...)
    Comparing the number of process steps (EUV vs immersion) seems to assume comparable throughputs. But actually you can have something like 4000 wafers/day immersion vs. 1000 wafers/day EUV (the EUV throughput depends on dose). So if you had 4 days for 4 passes, after 4 days 4000 wafers completed the layer with immersion quadruple patterning, while 2000 (1000+1000) wafers completed the layer with EUV double patterning. In memory, Samsung and others are using numerous ways to keep the number of masks to a minimum. It's a little easier because all the features are on a grid. For 3D NAND, they have stopped shrinking but actually still use double patterning, which we can imagine or surmise is still faster than EUV.

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    Last edited by Fred Chen; 4 Weeks Ago at 05:58 AM.
     

  6. #36
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    Quote Originally Posted by Fred Chen View Post
    Comparing the number of process steps (EUV vs immersion) seems to assume comparable throughputs. But actually you can have something like 4000 wafers/day immersion vs. 1000 wafers/day EUV (the EUV throughput depends on dose).
    That is the reason I was saying "assuming EUV is up for real production". So let's say instead of one fourth, only one half of the throughput.
    For NAND I see an interest, if one can shrink pitch again, of reducing the spacing vs augmenting the number of layers. Thanks for the useful debate.

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  7. #37
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    Quote Originally Posted by Daniel Nenni View Post
    Yes, I believe it is the Snapdragon 855. Here is the backstory in case you are interested:

    QCOM and TSMC were best friends until Apple came to TSMC at 20nm. With Apple as TSMC's best friend QCOM went to Samsung at 14nm. Samsung 14nm was very good so QCOM stayed for 10nm. Samsung 10nm was a catastrophe, it did not yield so QCOM jumped over to TSMC 7nm. That is QCOM in a nutshell by the way.
    QC's TSMC 20nm SoCs were the worst in the history of mobile semiconductors.
    I love how you omit the fact that QC went for a second generation SS 10LPP even though it was so bad. And how was 10LPE a catastrophe while being 6 months ahead to mass production compared to TSMC while performing the same as the latter?

    QC jumped to TSMC 7nm simply because for the release cycle of the 855 (Q1 2019) Samsung won't have 7nm volume production ready in time.

    Quote Originally Posted by Daniel Nenni View Post
    I'm really interested to see a benchmark between the 10nm an 7nm Snapdragons. The should be close to an apples-to-apples process comparison.
    Might as well benchmark a toaster against a microwave because those two generations won't have any common IP in-between them.

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