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Thread: Intel's 10nm launch is a PR stunt.

  1. #1
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    Intel's 10nm launch is a PR stunt.

    Is Intel's upcoming 10nm 'launch' real or a PR stunt? - SemiAccurate

    Can Intel's management team pull that off with no real consequence?

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  2. #2
    Admin Daniel Nenni's Avatar
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    If so it is one of the worst PR events Intel has done. I would be surprised if Intel management survived this one.

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    Now available in print or Kindle: "Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices"

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    Intel starts shipping first 10nm 'Cannon Lake' processor with 32GB LPDDR4 RAM support - The iBulletin

    "The dual-core Core i3-8121U sports the Cannon Lake architecture, but the integrated graphics are either disabled or not present. As a result, the notebook comes with RX540 graphics. We followed up with Intel, which confirmed that the chips are only on sale in China."

    "For now, the Core i3-8121U will be Intelís primary unit as it improves its 10nm process."

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    Dual core only... What is the size of this chip?

    Dual core with GPU was 82mm2 at 14nm, half of that was GPU so we can assume 41mm2 for CPU part. Here is summary with die photos and measurements:

    Broadwell - Microarchitectures - Intel - WikiChip

    If we will believe that Inted did not lied about full microprocessor die area scaling (note that there is specifically mentioned entire die with both SRAM, logic and IO) as seen on image bellow:

    Then this dual core part will be only 17.63mm2 big (or 35 if they manufacture it with GPU). So 10nm must be even harder to manufacture than expected (first parts at launch stage of other processes were usually around 80-120 mm2 for every foundry, 17mm2 is smaller than lot of test vehicles i have seen).

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  5. #5
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    Rumor says it's a 2+2 die: 2 CPU cores + 24 GPU EUs, only that the GPU part is disabled (or most probably defective).
    Intel displayed a canon lake wafer. Manual counting puts the wafer at around 36 dies across and 35 dies down, which leads to a die size of around 8.2 mm by 8.6 mm, or ~70.5 mm2 per die.

    The equivalent 2+2 skylake die is ~101.83 mm≤. So, either canon lake has significantly more transistors or real life scaling is way lower than what Intel claims.

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  6. #6
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    It so happened that my urge to write a short post with a few comments to this article by Charlie grew into something else. You can check the result here.

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