You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!




Page 1 of 5 123 ... LastLast
Results 1 to 20 of 85

Thread: Intel 7nm on track

  1. #1
    Member
    Join Date
    Oct 2016
    Posts
    33
    Thumbs Up
    Received: 12
    Given: 3

    Intel 7nm on track

    This looks very interesting! With it being a completely separate team and effort from their 10nm. I think Intel will quickly go back to being on top. I simply don't see them letting AMD run off with it for long.

    Intel: EUV-Enabled 7nm Process Tech is on Track

    1 Not allowed!
    Last edited by Daniel Nenni; 12-08-2018 at 03:33 PM.
     

  2. #2
    Expert
    Join Date
    Mar 2012
    Posts
    653
    Thumbs Up
    Received: 256
    Given: 215
    Quote Originally Posted by KingSeGa View Post
    Intel: EUV-Enabled 7nm Process Tech is on Track

    This looks very interesting! With it being a completely separate team and effort from their 10nm. I think Intel will quickly go back to being on top. I simply don't see them letting AMD run off with it for long.
    It's not surprising that they have a separate 7nm development team, but it's pretty clear it won't be happening soon, in particular if EUV is a focus. At the EUV workshop this year, Intel showed their 5 EUV tools got dirty pretty quickly, so they needed pellicles. Also, with 2x scaling, it means they will be at or beyond the 13 nm resolution spec limit of the NXE:3400, so they are likely focusing on the high NA tool. It's moot, since the fundamental resolution limiting issues for EUV are the stochastics (already bad at 20 nm feature size) and the travel distance of secondary electrons, which accounts for at least 2 nm of CD variation.

    3 Not allowed!
    Last edited by Fred Chen; 12-08-2018 at 03:06 PM.
     

  3. #3
    Member
    Join Date
    Oct 2016
    Posts
    33
    Thumbs Up
    Received: 12
    Given: 3
    Hi Fred
    So do you think maybe 2020 it'll be up and running?

    0 Not allowed!
     

  4. #4
    Expert
    Join Date
    Mar 2012
    Posts
    653
    Thumbs Up
    Received: 256
    Given: 215
    Quote Originally Posted by KingSeGa View Post
    Hi Fred
    So do you think maybe 2020 it'll be up and running?
    They would still be running 10nm if lucky.

    0 Not allowed!
     

  5. #5
    Top Influencer
    Join Date
    Aug 2013
    Posts
    235
    Thumbs Up
    Received: 63
    Given: 26
    In tech I'll believe it when I see it.

    1 Not allowed!
     

  6. #6
    Admin Daniel Nenni's Avatar
    Join Date
    Aug 2010
    Location
    Silicon Valley
    Posts
    4,677
    Thumbs Up
    Received: 1,167
    Given: 2,584
    Here is the problem:

    Murthy Renduchintala, chief engineering officer and president of technology, systems architecture and client group at Intel is quoted to have said at the Nasdaq's 39th Investor Conference:“7 nm for us is a separate team and largely a separate effort. We are quite pleased with our progress on 7 nm. In fact, very pleased with our progress on 7 nm. I think that we have taken a lot of lessons out of the 10 nm experience as we defined that and defined a different optimization point between transistor density, power and performance and schedule predictability. […] So, we are very, very focused on getting 7 nm out according to our original internal plans.”

    Coming from anyone else I would have a lot more confidence. I heard nothing about 7nm at IEDM last week but I did hear that Intel 10nm is doing well and will be in HVM in 1H 2019. Yield learning for sure so I hope it is true. I will be in Taiwan next week and will ask around a bit. I did confirm that Intel is officially out of the foundry business which was expected. Maybe we will learn more at SPIE in February.

    4 Not allowed!
    Last edited by Daniel Nenni; 12-08-2018 at 03:35 PM.
    Now available in print or Kindle: "Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices"

  7. #7
    Member
    Join Date
    Oct 2016
    Posts
    33
    Thumbs Up
    Received: 12
    Given: 3
    Is Murthy not a reliable source?

    Intel out of the foundry business? So they're only going to produce their own chips or design on TSMC or Samsung?

    0 Not allowed!
     

  8. #8
    Member
    Join Date
    Sep 2014
    Posts
    7
    Thumbs Up
    Received: 2
    Given: 5
    Hard to say where Intel really is, but this article is pretty naive. If Intel uses EUV it will not be on 10-20 layers - it will be 1-2 layers.

    0 Not allowed!
     

  9. #9
    Member
    Join Date
    Oct 2016
    Posts
    33
    Thumbs Up
    Received: 12
    Given: 3
    Isn't Samsung and TSMC using 4-5 layers? With Intel on 7nm it should beat out TSMC on 5nm?

    0 Not allowed!
     

  10. #10
    Top Influencer
    Join Date
    Aug 2014
    Posts
    366
    Thumbs Up
    Received: 183
    Given: 0
    Up until about 5 years ago, Intel wouldn't comment about technology development like this, they would simply demonstrate it with a SRAM test chip. Proof of life basically. Generally in the last few months of the year.

    Note there is no test chip, this year. Most likely next year.

    0 Not allowed!
     

  11. #11
    Blogger Scotten Jones's Avatar
    Join Date
    Oct 2012
    Location
    Greater Boston Area
    Posts
    638
    Thumbs Up
    Received: 309
    Given: 6
    Quote Originally Posted by Fred Chen View Post
    It's not surprising that they have a separate 7nm development team, but it's pretty clear it won't be happening soon, in particular if EUV is a focus. At the EUV workshop this year, Intel showed their 5 EUV tools got dirty pretty quickly, so they needed pellicles. Also, with 2x scaling, it means they will be at or beyond the 13 nm resolution spec limit of the NXE:3400, so they are likely focusing on the high NA tool. It's moot, since the fundamental resolution limiting issues for EUV are the stochastics (already bad at 20 nm feature size) and the travel distance of secondary electrons, which accounts for at least 2 nm of CD variation.
    At 10nm Intel has a CPP of 54nm, an M2P of 44nm, SDB and a 6.18 track cell height. 10nm was a 2.7x scaling from 14nm.

    Intel has previously said 7nm will be a 2.3x scaling although maybe that has now been relaxed to ~2.0x

    My forecast for a 2.3x scale was a CPP of 42nm (roughly the device limit for a FinFET) done with SADP (EUV lines are too rough for the FEOL), an M2P of 26nm (the limit for single exposure EUV but more on this later), SDB and a 5.5 track cell.

    No high NA needed. If Intel was planning on high NA they wouldn't be talking about 2020.

    I do think the 26nm M2P might be EUV LE2, EUV throughput is highly dose sensitive unlike DUV. We may see some EUV LE2 for aggressive pitches because 2 EUV 20mJ/cm2 exposures may be cheaper than one exposure at say 60mJ/cm2 or more.

    Having said all that, with 10nm really ramping in late 2019, 7nm in 2020 strikes me as aggressive. The specifications needed to get a 2.3x shrink will result in devices that are really aggressive and I think the device issues may be more difficult than the EUV.

    4 Not allowed!
     

  12. #12
    Top Influencer
    Join Date
    Aug 2015
    Posts
    148
    Thumbs Up
    Received: 138
    Given: 179
    Quote Originally Posted by Scotten Jones View Post
    At 10nm Intel has a CPP of 54nm, an M2P of 44nm, SDB and a 6.18 track cell height. 10nm was a 2.7x scaling from 14nm.

    Intel has previously said 7nm will be a 2.3x scaling although maybe that has now been relaxed to ~2.0x

    My forecast for a 2.3x scale was a CPP of 42nm (roughly the device limit for a FinFET) done with SADP (EUV lines are too rough for the FEOL), an M2P of 26nm (the limit for single exposure EUV but more on this later), SDB and a 5.5 track cell.

    No high NA needed. If Intel was planning on high NA they wouldn't be talking about 2020.

    I do think the 26nm M2P might be EUV LE2, EUV throughput is highly dose sensitive unlike DUV. We may see some EUV LE2 for aggressive pitches because 2 EUV 20mJ/cm2 exposures may be cheaper than one exposure at say 60mJ/cm2 or more.

    Having said all that, with 10nm really ramping in late 2019, 7nm in 2020 strikes me as aggressive. The specifications needed to get a 2.3x shrink will result in devices that are really aggressive and I think the device issues may be more difficult than the EUV.

    Intel is likely to ramp 10nm to high volume in H2 2019 with 10nm client systems available for holiday 2019. Whats likely to happen is the first chips will be ultra low power for tablets like Core M Broadwell which launched in Nov 2014. The mainstream 10nm notebook chips will launch in H1 2020 followed by desktop 10nm chips in late 2020 and server 10nm chips in early 2021. Intel is expected to launch another 14nm desktop generation Comet Lake in late 2019.

    Intel's Comet Lake-S Rumored to Pack 10 Cores, Debut on 14nm - ExtremeTech

    TSMC leads Samsung and Intel on all EUV progress metrics such as source availability, source power and is scheduled to start N7+ EUV HVM in Q2 2019. TSMC is using N7+ EUV to iron out the issues with EUV and prepare for a successful high volume ramp of N5 in Q2 2020. TSMC 5nm is on track for risk production in Apr 2019 and HVM in Q2 2020. I do not expect Intel 7nm to arrive in 2020. Intel is still talking of a 2x density increase wrt their 10nm which puts the density at 200 MTx/sq mm. Given that Intel 10nm will only ramp across all of its product lines in 2020, Intel 7nm is more likely to arrive by 2022 and compete with TSMC 3nm.

    3 Not allowed!
     

  13. #13
    Member
    Join Date
    Oct 2016
    Posts
    33
    Thumbs Up
    Received: 12
    Given: 3
    But Intel's 7nm to compete with what I'm sure TSMC will be using GAA at 3nm. The same as Samsung. Doesn't seem they'll be able to be competitive with AMD from process. I guess I could understand their 10nm woes. That's a very ambitious goal with the density target without EUV.

    2 Not allowed!
     

  14. #14
    Influencer
    Join Date
    Oct 2013
    Posts
    64
    Thumbs Up
    Received: 54
    Given: 129
    "I think that we have taken a lot of lessons out of the 10 nm experience as we defined that and defined a different optimization point between transistor density, power and performance and schedule predictability."

    This should probably read "lessons out of the 14nm and 10nn experience". And it may mean that 5nm Intel will not be equivalent to 3nm TSMC, metrics should even out as Intel runs to catch TSMC.

    1 Not allowed!
     

  15. #15
    Blogger
    Join Date
    Jan 2011
    Location
    The land of beer and chocolate
    Posts
    957
    Thumbs Up
    Received: 262
    Given: 342
    Quote Originally Posted by Scotten Jones View Post
    Having said all that, with 10nm really ramping in late 2019, 7nm in 2020 strikes me as aggressive. The specifications needed to get a 2.3x shrink will result in devices that are really aggressive and I think the device issues may be more difficult than the EUV.
    Delay in 10nm ramping does not mean that device development of 7nm would be delayed. So I do think timelines are not correlated.

    0 Not allowed!
    Trust me ...
    I know what I am doing.

  16. #16
    Blogger Scotten Jones's Avatar
    Join Date
    Oct 2012
    Location
    Greater Boston Area
    Posts
    638
    Thumbs Up
    Received: 309
    Given: 6
    Quote Originally Posted by KingSeGa View Post
    But Intel's 7nm to compete with what I'm sure TSMC will be using GAA at 3nm. The same as Samsung. Doesn't seem they'll be able to be competitive with AMD from process. I guess I could understand their 10nm woes. That's a very ambitious goal with the density target without EUV.
    My understanding is TSMC is likely staying with FinFETs at 3nm.

    1 Not allowed!
     

  17. #17
    Blogger Scotten Jones's Avatar
    Join Date
    Oct 2012
    Location
    Greater Boston Area
    Posts
    638
    Thumbs Up
    Received: 309
    Given: 6
    Quote Originally Posted by Staf_Verhaegen View Post
    Delay in 10nm ramping does not mean that device development of 7nm would be delayed. So I do think timelines are not correlated.
    I think it depends on what the 10nm yield issues are, if they are just lithography then it might be decoupled with the move to EUV but if they have device or material issues it might impact it.

    1 Not allowed!
     

  18. #18
    Top Influencer
    Join Date
    Aug 2015
    Posts
    148
    Thumbs Up
    Received: 138
    Given: 179
    Quote Originally Posted by Scotten Jones View Post
    My understanding is TSMC is likely staying with FinFETs at 3nm.
    Scotten it was my understanding that TSMC is planning a move to GAA at 3nm.

    TSMC Technology Roadmaps - Breakfast Bytes - Cadence Blogs - Cadence Community

    "Beyond FinFET, TSMC is planning horizontal nanowire, what they call gAA for gate-all-around. As the name implies, the source/channel/drain is built out of a number of wires running through the center of the gate giving even better control than FinFET. This is planned for 3nm. It has superior electrostatics for enhanced energy efficiency. Beyond FinFET they are also looking at germanium with Ge hGAA pFET that they have built having record performance (the picture showed a transistor using 4 nanowires"

    1 Not allowed!
    Last edited by Daniel Nenni; 12-10-2018 at 08:36 PM.
     

  19. #19
    Blogger Scotten Jones's Avatar
    Join Date
    Oct 2012
    Location
    Greater Boston Area
    Posts
    638
    Thumbs Up
    Received: 309
    Given: 6
    Quote Originally Posted by raghu78 View Post
    Scotten it was my understanding that TSMC is planning a move to GAA at 3nm.

    TSMC Technology Roadmaps - Breakfast Bytes - Cadence Blogs - Cadence Community

    "Beyond FinFET, TSMC is planning horizontal nanowire, what they call gAA for gate-all-around. As the name implies, the source/channel/drain is built out of a number of wires running through the center of the gate giving even better control than FinFET. This is planned for 3nm. It has superior electrostatics for enhanced energy efficiency. Beyond FinFET they are also looking at germanium with Ge hGAA pFET that they have built having record performance (the picture showed a transistor using 4 nanowires"
    We will see, I have sources who say they are trying to stay with FinFETs for 3nm and given that foundry 3nm is really around a 5nm process that is certainly achievable.

    1 Not allowed!
     

  20. #20
    Member
    Join Date
    Oct 2016
    Posts
    33
    Thumbs Up
    Received: 12
    Given: 3
    How do you feel if a customer would like to use 7nm from Intel? Would they block or delay the process even if it's available just to use 10nm for the time being?

    Also, does anyone find it strange that Samsung 7LPP EUV doesn't have any announced customers? When TSMC who seems to be behind them has said to have 100 customers by 2019 on 7nm and 7nm EUV?

    0 Not allowed!
     

Page 1 of 5 123 ... LastLast

Tags for this Thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •