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Thread: Best #48DAC Trip Report Gets an iPAD2

  1. #31
    Blogger Daniel Payne's Avatar
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    EDA Interoperability at DAC

    Intro
    My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.
    Click image for larger version. 

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    Notes
    Interconnect Modeling
    - Open Source Interconnect Technology Format (ITF)
    o Used by Star RC
    - Modeling parasitic of interconnect
    - Interconnect Modeling Technical Advisory Board founded, meet twice per year
    o Program of IEEE-ISTO
    o Andy Brotman, VP Design Infrastructure at GF
    IMTAB – foundry perspective
    Design starts are slowing in number for each new node (although each new node has more devices)
    Need to avoid risks, ensure 1st silicon success
    Mistakes are more costly (NRE)
    Parasitic variation increases at 20nm, more analysis required
    Layout effects need to be simulated earlier
    Best in class extraction tools are a must
    Standard interconnect tech file used (Star RC, F3D, …)
    New layout effects: Orientation dependent width bias
    o Rich Laubhan, Engineer and Manager of Signal Integrity at LSI Corporation
    User perspective (Used Star RC for 13 years now)
    LSI products: HDD controllers, SSD controllers, RAID adapters, networking
    Producing 65nm, 40nm, 28nm chips
    Many signoff PVT/RC corners
    • No real single corner to simulate
    Many modes to simulate: functional, scan, BIST, TDF
    High speed designs: 500MHz to 2GHz clocks
    Can have 200 clock domains
    Hierarchical designs with 20M instances
    Plot of transistor feature size and number of metal layers (12 layers now)
    ITRS plot: total metal interconnect on a chip over time, more resistive effects
    No standard test structures to measure R L C values
    We use Charge based capacitance measurement (CBCM)
    More wires, higher resistance, metal fill effects: designer challenges
    LSI Design Flow: Tech File and Design input to Parasitic Extraction, output a SPICE Or SPEF file
    • Tech file: cross section, dielectrics, vias, R L C values
    Tech File Complexity: IC Cross section with 12 metal layers, dielectrics
    • Longer qualification time to meet accuracy goals
    • Variation in process causes variation in R L C values
    ITF Open source – provides a proven format with support from 130nm to 20nm
    ITF Extensions proposed
    • Quick process to get ratified
    • Layout dependent effects
    • TSV
    • 28nm and 20nm effects
    Desire to use fewer EDA tool formats to keep costs lower
    • Changed extraction tools three times for last three technology nodes
    Challenges
    • Agreement on test structures
    • Accurate results
    Tenzing Norgay Award
    - Surpass common levels of interoperability
    - Contribute to overall industry advancement
    - Provide a new view of the future
    - 2011 Winner: Shreink Mehta
    o Work on UPF, SystemVerilog
    o Sun SPARC
    o OVI and VHDL
    o SPIRIT


    IPL & Custom Design
    - IPL Constraint 1.0, first standard for interoperable analog design constraints
    - OPDK and iPDK are cooperating
    - Vincent Varo, Process Design Kit Manager, STMicroelectronics
    o Desire to reduce effort in PDK development, create one PDK not many, use across all EDA tools
    o Device Library, DRC, LVS, PEX, SPICE
    o Standardized input to PDK development process from all foundries desired
     Standard DRM, Device Specification format
    o Challenge: How to validate an automatically created PDK?
    o Mulitple methods to create a single iPDK
    o Parasitic Extraction technolog file
     IMTAB, or Si2 OPEX WG
    o Desire to be EDA Tool independent
    o Next steps
     Automate the PDK validation process
     Design re-use and portability
     AMS design portability
     Designs that are DRC and LVS clean by construction
    - Ori Galzur, VP VLSI Design Center, TowerJazz
    o Largest foundry for speciality technologies
    o Total of 4 foundries: Newport Beach, Japan, Israel, China
    o Approaching $1B in revenues
    o Power, BiCMOS, SiGe, RF CMOS, Image Sensor, Mixed-Signal CMOS, eNVM
     1um to .13um
    o Specialty PDK for high voltage process
     Automatic device scaling based upon the voltage levels that you need
     ESD rules added to PCELL
     From schematics a designer gets to choose from a GUI all of the device parameters
    o Average PDK has over 120 devices
    o Each device can be used in: Standard, Shallow NBL, Deep epi
    o All devices are voltage scalable, optimized
    o Supporting multiple tool sets takes too much engineering effort
    o Want one PDK to focus engineering on other value add efforts
    o Choose the best foundry, best EDA tools, not locked into a vendor-specific PDK
    Summary
    - Demand that your Foundry and EDA vendors support iPDK

    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

  2. #32
    Blogger Daniel Payne's Avatar
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    Ciranova Update at DAC

    Intro
    Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.
    Click image for larger version. 

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    Notes
    New in 2011
    - New GUI with schematic, layout and constraints
    o Cross probing between all three windows
    - Schematic for constraint entry
    o Can start with a blank schematic, enter new design
    o Read any native OA schematic
    o See all the MOS instances in a tree, define layout constraints very quickly
    o Drag and drop constraints
    o Cross probe between MOS list and Schematic view
    o Hierarchy supported
    - Helix First Look
    o Schematic and Analog constraints in, layout out
    o Find in netlist common bulks, get placed together
    o Easy way to create initial layout constraints, does auto grouping of layout
    - New customers: Marvel
    - 28nm migration is important, Helix is an easier way to conform to new design rules
    o Auto placement helps on minimum rules
    o Read design rules for density and Helix can push transistors apart to reach the rules
    - Create many alternative layouts, Extract a netlist, use Calibre parasitics, create fully extracted netlist ready for Berkeley AFS
    - Users: Initially the Circuit Designer starts, then handed off to the Layout Designer for completion
    - Routing Example: pattern based constraints used, then autoroute between all the rows and columns of placed Devices
    - New way to create layout constraints, based on patterns or Python scripts (mostly CAD or Circuit Designers create scripts)

    Summary
    Ciranova Helix is a tool that can create analog layout using PyCells very rapidly by a Circuit Designer. Demanding IC designers from the largest semiconductor companies in the world use these tools.

    Last edited by Daniel Payne; 06-19-2011 at 06:20 PM.
    Daniel Payne, EDA Consultant
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    503.806.1662

  3. #33
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    RLCK reduction tool at DAC

    Intro
    Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.
    Click image for larger version. 

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    Daniel Borgraeve (on right)

    Notes
    Edxact
    - Started seven years ago
    - Fifteen people in the company
    - Based in France
    - Jivaro: RLCK reduction (RLCC) with user control of results
    o Many algorithms to choose from
    o Used by Aglient in their GoldenGate tool (RF Simulator)
    o Used by Intel
    o About 25 customers world wide (Asia, Japan, Korea, US)
    o Part of TSMC AMS Reference flow 2.0
    o Pricing starts at $100K per license per year
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    - Comanche:
    o Read parasitic
    o Create R values point to point, calculate delays
    o CAD developers can compare two netlists (Golden versus some extraction tool)
    o Parasitic analysis platform
    o Used by: AMD, ST Ericsson
    o Pricing starts at $100K per license per year
    - Partners
    o Altos (Library Characterization, used Jivaro)
    o Cadence (Integrated into Virtuoso)
    o SpringSoft (Integrated into Laker, can annotate parasitic into Laker)
    o Mentor (read DSPF, Eldo formats)
    o Synopsps (support Star RC and HSPICE syntax)
    o TSMC – part of AMS Reference flow
    - Runs on: Solaris, Linux, Mac

    Summary
    If you want more control while reducing RCLK netlists then consider looking at Edxact tools.

    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

  4. #34
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    Cadence spinout at DAC

    Intro
    I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.

    Notes
    Proplus – US company, founded in 1995 (Used to be Celestry, acquired by Cadence, spun out in 2007)
    - R&D in Beijing and Silicon Valley
    - NanoDesigner (4 years old): SPICE tool, not Fast SPICE
    o Compete with: Spectre, FInesim, HSPICE
    o Accuracy is the goals
    o Statistical SPICE (Monte Carlo technique)
    o Customers: Not disclosed
    o Pricing: Not disclosed
    - IR/EM Verification
    o Partnership with Grid Simulation Tech
    o Customers: Not yet
    Summary
    I hadn't heard of Proplus before last week, so I've added it to the list of all SPICE tools on our wiki page.

    Daniel Payne, EDA Consultant
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  5. #35
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    Reduced IC leakage at DAC

    Intro
    Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.

    Notes
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    Why do this?
    - Reduce leakage
    - Increase gate lengths on paths with slack
    - Recharacterize cells for change channel length, new performance
    - Take the output from Primetime for paths with slack
    - Our tool also has a timing engine built into it
    - Fine grain optimization for leakage optimization
    - Our tool does more cell swaps than other tools do
    - Can swap multi vt cells as well
    - TSMC has four Vt choices, but with gate biasing you have finer control than just swapping Vt
    - Gate biasing doesn’t require another mask
    - Optimize for: Performance, leakage, costs
    - At 28nm the PowerTrim libraries should become more mainstream
    - At 40nm, you can bias the gate length to optimize as well
    - Another technique for 28nm is to start with 35nm then use gate biasing
    - Customers can ask for design services from Tela, or ask TSMC to use PowerTrim
    - Customers: LSI Logic, Melanox, undisclosed (over 50 tapeouts so far)
    - Gate biasing can make the device go faster (more leakage) or slower (less leakage)

    Summary
    If you fab with TSMC and want to reduce your leakage currents, then consider the PowerTrim library approach.

    Daniel Payne, EDA Consultant
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    503.806.1662

  6. #36
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    Circuit Simulation update from Cadence at DAC

    Intro
    In the bloggers suite I met with John Pierce of Cadence last Wednesday to get an update on what's new with circuit simulation at DAC this year.

    Notes

    News – market is growing, RF CMOS simulation is growing
    - Show on RF (MTT – Microwave Technology ) this week, sharing a booth with AWR this week
    - Recent news with Lorenz (EM tool to create inductors), they’re part of Connections program
    - APS RF released on year ago (Parallel in the new engine)
    - RF usability improved, able to do s-parameter analysis

    Virtuoso APS – continued to improve, up to 16 cores
    - December 2010 now you can go distributed, across machines
    - No special setup required
    - Uses more tokens
    - Super Threading: multi-core plus distributed processing (multi-core per box)
    - Typical usage: Two machines, 4 cores per machine

    UltraSim – looking at next generation technologies
    - Usability and speed improvements done and planned
    - New developers added
    - Did a new RF model

    Modeling – how to model FInFET (Tri-gate)?
    - Compact Modeling group involvement

    Altos – acquired library characterization company
    - Integrated with them last year, especially memory characterization
    - Works with either Spectre or UltraSim or internal simulator

    Growth – Altos had 11 out of 20 top semi companies for library characterization
    - Good collaboration over past 12 months too (Jim Mccanney)


    Spectre – New in last year is APS and distributed
    - Shares models with UltraSim

    AMS Designer – transistor simulation plus HDL
    - Real number modeling (standard part of SystemVerilog) lets you model analog effects in a logic verification environment
    - Did a paper at the ARM conference last year, DVCON this year (assertions plus real number modeling)
    o Help ADC test bench verification
    - Adoption of real number modeling is driven by the design style more than the technology
    - Work with designersguide.com on training the next generation of AMS designers, classes tailored to the client and offer consulting services
    - Knowlent went out of business as Analog Verification IP (too limited of an approach, not portable)
    - How to influence the next generation, Universities

    Parasitic Aware Design – simulation with real parasitic, as early as possible in the flow
    - Quickly go from schematic to layout to extracted parasitic, better simulation results
    - Virtuoso can help manage the whole parasitic flow

    IMS Chips (Germany) – Used Custom Designer, then went back to Virtuoso (Feb 2011)

    Wolfson (UK) – Uses SNPS digital tools, and internal analog tools. They evaluated Custom Designer but choose Virtuoso plus digital flows.

    Summary
    Cadence has plenty of competitors in the circuit simulation space so they continue to update and innovate their tools to stay current. Only three vendors offer an integrated co-simulation between SPICE and a widely-adopted HDL simulator (Cadence, Mentor, Synopsys).

    Daniel Payne, EDA Consultant
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    503.806.1662

  7. #37
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    Hardware Configuration Management at DAC

    Intro
    Show me what has changed in my RTL or Schematic since the last time I looked. This task is now automated by Cliosoft with their new hierarchical tool called Visual Design Difference (VDD). Srinath showed me what was new for DAC.

    Best #48DAC Trip Report Gets an iPAD2-anantharaman_headshot.jpg
    Srinath Anantharaman

    Notes
    LSI, STMicro – use DesignSync for their DM but use VDD for seeing visual differences.
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    Visual Diff – Tool introduced just over one year.
    - This year it handles hierarchy.
    - Can also ignore Cosmetic Changes that have no electrical changes.
    - If you make changes to your RTL design, then how do you see what has changed?
    - Demo: Compared two versions of a design
    o Tree widget shows the hierarchy of where to find the changes
    o Expand the tree widget, see each difference in logic
    o See changes in different colors
    o Zoom on changes per pin or net, complete text description
    o Standard feature at no extra cost for existing customers
    o Can even see property changes along with logical changes
    Clients: Virage – started with Springsoft Laker, then Virtuoso, now Custom Designer (stayed with Cliosoft DM throughout)

    Summary
    If your IC design team has two or more engineers then your job will be made easier with a tool like VDD from Cliosoft.

    Daniel Payne, EDA Consultant
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    503.806.1662

  8. #38
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    An Affordable 3D Field Solver at DAC

    Intro
    Massimo Sivilotti, Ph.D of Tanner EDA showed me their 3D field solver in the HiPer PX extraction tool at DAC last week.
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    Notes
    Best #48DAC Trip Report Gets an iPAD2-screen-shot-2011-06-17-4.29.10-pm.jpg
    Tool Suites – schematics, layout, SPICE simulation, DRC/LVS
    - HiPer PX: 3D Field solver
    o Layers, dielectrics,
    o Finite element analysis
    o Boundary element methods
    o 2D mode for pattern matching
    o PDK – includes the info for PX extraction
    o 3D viewer to see the IC Layout
    o Offered for a few years now
    o Extract: Devices, parasitic, interconnect
    o Produces RC netlist (not L, not s-parameters), coupled C
    o Take parasitic from PX extraction then view it in Schematic editor (S-Edit)
     Swap out cell parasitics by changing the view
    o Run times are more limited by your simulator, not the extraction
    o Built-in netlist reduction algorithms (supply a frequency range), typically the reduced netlist is 10% the size of the original netlist
    o Not a multi-core algorithm yet (T-Spice is multi-core for circuit simulation)
    o Developed at TU Delft in Europe, licensed technology
    o Runs on both PC and Linux (32 or 64bit)
    o Comparable accuracy with Assura RX
    Licensing – Sentinel
    - Dongles
    - Commuter
    - Time-based
    - Rentals
    - Even permanent licenses

    L-Edit – used for stacked die layout with IC and Mems
    - Packaging techniques to locate all pads


    3D Solid Modeler
    - Used for MEMS Design – have a solid modeler (air or dielectrics)
    - Interfaces to Finite Element Analysis
    - Optical example with mirror

    Summary
    Tanner EDA continues to offer affordable IC design tools, HiPer PX offers both 3D and 2.5D extraction depending on the accuracy that you need.

    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

  9. #39
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    DRC tool guns for Calibre at DAC

    Intro
    Across the aisle from the Mentor booth at DAC sat a DRC tool competitor to Calibre. I received an update from Randy Smith of Polyteda on Wednesday afternoon, my last EDA vendor of the week.
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    Ravi Ravikumar, Randy Smith

    Notes
    Randy Smith – CEO (February 2011) [former founder is gone]
    - 1979 at HP developing internal tools
    - Trilogy
    - Tangent, Acquired by Cadence
    - Bought 4 times
    - Celestry->Cadence
    - Gambit->Synopsys
    - Japan consulting business
    Before – big performance claims

    Now – about 2 to 3X faster than Calibre while running in flat mode, PowerDRC
    - Look for a new hierarchical announcement by end of year, look for a new name
    - Smaller memory footprint
    - Easy to scale across multi-processors
    - TSMC has a reference flow, while larger companies can use a new DRC tool during design process
    o 3 way NDA between: Polyteda, TSMC, Client. Tune the rule deck. 40nm deck. Takes 18 months to reach sign off, stay tuned.
    - OEM relationship with AWR – single CPU limitation
    - IHP – customer, AMS client at 180nm (Pricing of Calibre seems too high)
    - Price/Performance – produce more results with less cost than Calibre
    - Learning curve: batch oriented, easy to learn, debugging is more of the issue, something similar to RVE called RDE (still internal)
    - Time based licensing, tied to the number of CPUs
    - Mentor has two licenses: Flat or Hierarchical
    - Polyteda will have one license: Flat and Hierarchical
    - Over 40 people in the company
    o R&D in Moscow
    o HQ in Santa Clara
    Summary
    Polyteda has reset expectations about their DRC tool performance and will have to battle against the entrenched Calibre in the marketplace. Competition always benefits the EDA tool users who need every advantage to get to market quickly and have first silicon success.

    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

  10. #40
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    Circuit Simulation and IC Layout update from Mentor at DAC

    Intro
    On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what's new at DAC this year in circuit simulation and IC layout tools.
    Attachment 1342

    Notes
    IC Station – old name for IC layout tools

    Eldo – Eldo Classic
    - Cell characterization
    - ST is the early customer and teaching customer, their Golden Simulator
    - Widely deployed worldwide
    Eldo Premier (January 2011 introduced, free transition from Eldo customers, new option, uses 2X the licenses)
    - Multi core, multi cpu
    - Accuracy driven
    - More accurate than Berkeley (they focus on PLL)
    - FineSim from Magma
    - XA from Synopsys
    - Developed in Grenoble, all new kernel, native MT
    - Average of 2.5X faster than Eldo at same accuracy, up to 20x faster
    - Input netlists: Eldo, HSPICE
    - Some analysis missing in Premier and will be released in next 12 months
    - DAC Session at 9AM on Tuesday AM
    ADiT – Fast SPICE simulator
    - Analog blocks up to 50 Million devices
    - Adding new capabilities
    - MediaTek standardized on ADiT
    - Similar to other Fast SPICE tools
    - Macro tuning capability and new partitioning in development
    Questa ADMS – Single kernel AMS simulator
    - Number one or two market share per EDAC, Gary Smith EDA
    - Close to Cadence in market share
    Grenoble – Eldo/Eldo Premier R&D
    Taiwan – ADiT team/Design Kits
    Armenia – CICD R&D
    Cairo – models, PDK
    Fremont – Division Headquarters
    Wilsonville – Custom IC Design R&D
    Austin – Custom Router R&D


    Innovate In IC physical design, stay close to silicon design.

    Technical Advisory Board – multiple initiatives
    - Quarterly meetings
    Simulators – all work within Cadence Virtuoso (Artist Link)

    Analog within Intel microprocessors

    Challenges
    - Variability (Physical, Electrical)
    - Design Risk, AMS is 75% of the risk for failure and cost for design and verification
    - Need MS verification (SPICE, HDL, Analog HDL, RTL)
    - Questa AMS (Analog Real Number modeling)


    Questa ADMS – C/C++, Matlab, VHDL-AMS, …

    IC Station (Version 9) – New name is: Pyxis Custom IC Platform (Version 10)

    Pyxis – OA database compliant (available now)
    - OA native for some functions
    - Schematics, Layout, Floorplanning
    - Launch simulators
    - Concurrent design, multiple designers can edit in the sam cell at the same time
    - Custom router
    - Multiple designers can edit in the same cell at the same time
    - Interface with Clio Soft
    - Can be used on LAN, not so tested on WAN yet
    - Custom Router (Native OA), easily go back and forth
    o Transistor, Cell, Block, Chip, Proven (Used at Marvell) [not related to Olympus – big digital, different division]
    o Interactive or batch routing
    o Uses Calibre RealTime deck, good integration

    Design Kits – founding member of IPL
    - Part of Open PDK
    - Can help to translate Development Kit formats
    - Pcell translator: Robust, accurate, fast (1 foundry, 1 customer using it too)
    - Create new PDK’s in a few weeks, able to QA libraries quickly


    Summary
    Mentor updates their tools for IC layout through the Pyxis acquisition and enhances circuit simulation with a speedier Eldo Premier. AMS co-simulation between HDL and SPICE simulators is a strong point for Mentor.
    Attached Thumbnails Attached Thumbnails Best #48DAC Trip Report Gets an iPAD2-lindafosler_mentor.jpg  
    Last edited by Daniel Payne; 06-22-2011 at 12:08 PM. Reason: corrections
    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

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