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Thread: ASML Q2-2018 results: Continued EUV Progress Enables ASML Roadmap Acceleration

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    ASML Q2-2018 results: Continued EUV Progress Enables ASML Roadmap Acceleration

    Earnings Growth Continues, Driven by Strong Sales Across Full Product Portfolio - Continued EUV Progress Enables ASML Roadmap Acceleration

    VELDHOVEN, the Netherlands, July 18, 2018 - ASML Holding N.V. (ASML) today publishes its 2018 second-quarter results.

    • Q2 net sales of EUR 2.74 billion, net income EUR 584 million, gross margin 43.3 percent
    • ASML expects Q3 2018 net sales between EUR 2.7 billion and EUR 2.8 billion and a gross margin between 47 percent and 48 percent


    CEO Statement
    "Our second quarter sales were above expectations including higher than forecasted EUV sales. Gross margin was slightly above our guidance, reflecting the strength of our DUV and Applications business and progress in EUV profitability.
    In Q2 we shipped four EUV systems, one more than we forecasted, as Logic customers prepare for the ramp of next node devices starting later this year. We recognized revenue for seven EUV systems. We are on track to supply 20 EUV systems this year. Focused execution is enabling an acceleration of the availability and productivity roadmap. This will provide an even stronger foundation for our EUV business and will support a 2019 shipment plan of at least 30 systems.
    Our DUV business is driven by a memory market that continues to require a significant number of lithography systems at least throughout this year and into 2019.
    After an excellent first half of 2018, we expect the second half to be stronger, with improved profitability and continued growth from Q3 to Q4," said ASML President and Chief Executive Officer Peter Wennink.

    ASML: Press - Press ReleasesEarnings Growth Continues, Driven by Strong Sales Across Full Product Portfolio - Continued EUV Progress Enables ASML Roadmap Acceleration - Press ReleasesEarnings Growth Continues, Driven by Strong Sales Across Full Product Portfolio - Continued EUV Progress Enables ASML Roadmap Acceleration

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    It looks like Samsung probably got its full order of 10 of the 17 NXE:3400 tools shipped so far. At the EUVL workshop Intel indicated it had 1, and GlobalFoundries has 2, so it leaves 4 for TSMC. There are of course older NXE:33x0 systems with more limited capabilities.

    Update: Naver (?? ????, 6?? ??? ??? : ??? ??) reported last year that Samsung actually planned to install 9 NXE:3400B tools, 2 last year, 7 this year. With 22 total NXE:3400B installed by Q3, we have 2 for GlobalFoundries, 9 for Samsung, then the remaining 11 split between TSMC and Intel. If Intel sticks with its one, then TSMC will have 10. That would imply TSMC would take all 5 NXE:3400 deliveries in Q3, if Samsung took the 7 from Q1+Q2.

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    Last edited by Fred Chen; 4 Weeks Ago at 06:37 PM. Reason: Update on EUV tool orders
     

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    Does this imply anything relative to the 40wph issue? Is Samsung using these for memory? At 40wph they would need more than 10 to be of much impact, especially if the wafers needed more than one pass.

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    Along the same lines, if Intel has one EUV machine and they take forever to make and install and ASML makes 20 this year, at 40wph what can intel really do with these that matters? The volumes just seem like a joke.

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    Perhaps it is of interest to some reading this thread to browse/study the various slides/lectures of the recent EUVL workshop, June 11-14, 2018, CXRO, Berkeley, CA.

    The proceedings of that workshop can be viewed at this link from which an easy click in this pdf program brings you to the slides of all the lectures:
    www.euvlitho.com/2018/2018%20EUVL%20Workshop%20Proceedings.pdf

    For instance, the public perspective of INTEL on the status of EUV for HVM can be browsed in the keynote lecture by Britt Turkot:
    Current status, challenges, and outlook of EUVLithography for High Volume Manufacturing
    www.euvlitho.com/2018/P4.pdf

    Everyone can evaluate the conclusions of INTEL's Turkot for themselves.

    The 2018-EUVL Workshop Proceedings have many interesting talks/slides on the June 2018 status of the EUV ecosystem for HVM and beyond.

    UserNL

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    Quote Originally Posted by Chipper View Post
    Does this imply anything relative to the 40wph issue? Is Samsung using these for memory? At 40wph they would need more than 10 to be of much impact, especially if the wafers needed more than one pass.
    40 WPH @250W corresponds to 100 mJ/cm2 dose, which could be to cover stochastic risks. They need to get to 1e-11 level (~100 billion contacts). I imagine 10 7LPP layers for EUV (M0-M4, CON-V4), so each layer could get a dedicated tool. With uptime of ~80% per tool, we might estimate the EUV line uptime to be (0.8)^10 ~10-11% but this assumes no correlations among the tool uptimes, which is probably wrong. With the line throughput of 1000 wpd, or 30K wafers per month, this is negligible compared to its DRAM output.

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    Quote Originally Posted by Chipper View Post
    Along the same lines, if Intel has one EUV machine and they take forever to make and install and ASML makes 20 this year, at 40wph what can intel really do with these that matters? The volumes just seem like a joke.
    Intel (and TSMC) will get more tools probably. Again, probably the same 10 layers targeted would mean at least 10 tools needed. Otherwise, fewer EUV layers means still some, maybe even most layers get multipatterned.

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    Last edited by Fred Chen; 4 Weeks Ago at 06:14 AM.
     

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    The transcript gives some more interesting details:

    - NXE:3400C EUV system to be introduced in 2019
    - 5 EUV tools to be shipped Q3 (following 3 in Q1 and 4 in Q2)
    - NXT:2000 DUV system to ramp in H2 due to strong customer demand in both memory and logic
    - More DUV immersion tools being sold in Q1+Q2 than EUV (40 vs. 8)

    ASML Q2-2018 results: Continued EUV Progress Enables ASML Roadmap Acceleration-asml-q2-2018-sales.jpg

    Source: Access to this page has been denied.

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    Last edited by Fred Chen; 4 Weeks Ago at 03:45 PM.
     

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    20 minutes into their Q2 call TSMs Che Chai Wei said: "we have the secured the largest number of EUV tools among our peers to be ready for 2019 volume production for N7+ and 2020 volume production for N5." Now "secured" does not mean "installed" but if 2019 is the time that really matters here and we have 17 tools out now, with 10 more scheduled this year and say 15 more by this time next year, that puts us at 42 EUV tools of all stripes on the planet split between 3 customers according to ASML (they said they have 3 in their Q2 call). That means TSM will have to have upwards of 20 machines by then assuming GF and Intel remain bit players. Does that sound plausible? To get there they would have to take practically everything ASML makes in the next 12 months. That sounds at odds with their capex reduction. Also it sounds like it is the NXE:3400B that matters here. Not sure when that was introduced.

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    Quote Originally Posted by Chipper View Post
    20 minutes into their Q2 call TSMs Che Chai Wei said: "we have the secured the largest number of EUV tools among our peers to be ready for 2019 volume production for N7+ and 2020 volume production for N5." Now "secured" does not mean "installed" but if 2019 is the time that really matters here and we have 17 tools out now, with 10 more scheduled this year and say 15 more by this time next year, that puts us at 42 EUV tools of all stripes on the planet split between 3 customers according to ASML (they said they have 3 in their Q2 call). That means TSM will have to have upwards of 20 machines by then assuming GF and Intel remain bit players. Does that sound plausible? To get there they would have to take practically everything ASML makes in the next 12 months. That sounds at odds with their capex reduction. Also it sounds like it is the NXE:3400B that matters here. Not sure when that was introduced.
    I have only tracked NXE:3400B since the NXE:3300 and NXE:3350 tools were reported by ASML to be more limited in terms of illumination options and throughput associated with those options. Also those earlier tools have larger aberrations. Finally, the NXE:3400 has the Dynamic Gas Lock membrane option to protect from outgassing from the wafer. The older tools are dirtier, as reported by Intel at the EUVL workshop.

    In 2019, the NXE:3400B will apparently be replaced by NXE:3400C.

    I had updated the following to my first post in this thread. Samsung was scheduled to receive 2 last year, and 7 this year. We might assume Samsung got the 7 total in Q1 and Q2 in order to be ready for EUV in 2018 H2. ASML reported the coming quarter Q3 will see 5 tools shipped, those could go to TSMC. Assuming Intel stays with one tool, and GlobalFoundries two, then TSMC would get those 5 added to their present 5, to get 10 total NXE:3400 by end of this quarter, which might be the basis of their claim (they would have more than Samsung's 9).

    The 20+ EUV tools after Q3 this year until next year would be split among Intel, Samsung, and TSMC. GF reportedly has space for 4 presently. If Intel and GF are out, then Samsung and TSMC would each have around 20 NXE:3400. Two NXE:3400 tools per layer would provide ~2000 wpd.

    To keep the perspective though, we need to also note that immersion tools (~6000 wpd) have also been shipping, in much larger quantities, as noted by these sales reported by ASML:

    Q3 2017: 4 EUV, 22 ArFi
    Q4 2017: 5 EUV, 20 ArFi
    Q1 2018: 1 EUV, 21 ArFi
    Q2 2018: 7 EUV, 19 ArFi

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    Last edited by Fred Chen; 4 Weeks Ago at 05:03 PM.
     

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    I got some more information on the older systems, the NXE:33x0. A total of 14 of these were shipped prior to the NXE:3400B, according to Wikipedia. Since these could be upgradable, I'll include them now.

    At the 2013 EUVL Workshop, it was mentioned Samsung to receive 2, SK Hynix to receive 1.
    At the 2018 EUVL Workshop, Intel listed defect data for 4 NXE:33x0.
    IMEC has been doing its research on 1.

    The remaining 6 are assumed to be TSMC.

    So my total EUV 0.33 NA tool estimate, projected as of Q3 2018, which could of course be wrong, is:

    TSMC: 6 NXE:33x0 and 10 NXE:3400 (total=16)
    Samsung: 2 NXE:33x0 and 9 NXE:3400 (total=11)
    Intel: 4 NXE:33x0 and 1 NXE:3400 (total=5)
    GF: 2 NXE:3400 (total=2)
    SK Hynix: 1 NXE:33x0 (total=1)
    IMEC: 1 NXE:33x0 (total=1)

    Of course, the distribution of immersion tools is a hazard to guess.

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    What happened with this 2015 order by INTEL:

    ASML reaches agreement for delivery of minimum of 15 EUV lithography systems

    VELDHOVEN, the Netherlands, 22 April 2015 - ASML Holding NV (ASML) today announces that it has signed an agreement with one of its major US customers to deliver a minimum of 15 ASML EUV lithography systems to support increased development activity and pilot production of future-generation manufacturing processes. The customer intends to use EUV lithography for multiple processing steps in future process technology nodes. The delivery of the first two NXE:3350B EUV systems is expected before the end of 2015. The new systems will be in addition to the existing EUV development systems already at the customer. Financial terms were not disclosed.

    ASML: Press - Press ReleasesASML reaches agreement for delivery of minimum of 15 EUV lithography systems - Press ReleasesASML reaches agreement for delivery of minimum of 15 EUV lithography systems

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    ASML put up a very solid quarter coming in at EUR 2.7B in revenues and EPS of EUR 1.26, GM was 43.3%. Guidance is for flattish EUR 2.7-2.8B but much better GM of between 47 and 48%. It is clear that the EUV drag on GM is going away as we come up the very long learning curve on the product.

    Four EUV systems were shipped versus 3 expected and the company is on track for the 20 systems it expects to ship in 2018.

    The company did talk about some push outs and pull in of orders in the memory space but it sounded like it was within normal ranges and the net result was little or no impact on the results as the company guided for a stronger H2 versus H1.

    In our view ASML is somewhat immune or resistant to near term capacity throttling in memory as most customers do not want to cancel or delay long lead time, more critical, litho tools versus other tools.

    There were no specific announcements regarding EUV which continues to make progress in the market.

    DUV remains a solid driver
    With all the talk of EUV we think it needs reminding that ASML's DUV business remains the workhorse driving the majority of the companies business. Yet another generation of the product was released and it is the solid underpinnings of DUV that supports the more difficult EUV efforts. The service business, based mainly on DUV tools as well as ongoing upgrades, has also become a significant driver and more steady business contributor.

    Outlook flat but probably conserrvative
    While revenue outlook is flat, the improving gross margins will continue to lift earnings. The guidance is flattish which may wind up being conservative but is likely correct given some near term gyrations in the memory market. Given the relatively large, lumpy EUV business where one or two tools can significantly impact revenues it is also a good idea to remain cautious given that shipments can slip for many reasons.

    Orders down but backlog solid
    Orders were down from EUR 2.442B to EUR 1.952 and saw a 3 unit drop in systems. We still think that the solid backlog will allow the company to continue to ship at a relatively steady rate. There could have been some slow down by Samsung in the order book but we think it has minimal impact given demand and lead times for systems. Litho is not a "turns" business like dep and etch which see more quarterly variation.

    EUV marches on
    The industry continues its decades long march towards EUV. Problems get solved and new ones crop up. There is still a long list of issues and reliability is still far from perfect but progress continues to be made. Resist, reticles and reliability remain as key points. It still feels like 5NM will be the "real" inflection point with 7NM as more of a test bed. One of the main drivers of EUV is the economic savings of fewer steps in the process and we are still not at an overwhelming advantage that would push chip makers over the top to a full EUV conversion. It remains not a matter of if but when, and we get closer all the time.

    Stock reacts positively after removal of fear factor
    Its clear that the stock has and will experience a "relief rally" as fears of a memory related drop off has kept pressure on the group. We did not expect a significant memory impact on ASML simply because of the business they are in.

    We have been clear that the majority of the impact will be felt by Lam followed by AMAT then KLAC then ASML with little to no impact. In the near term we see no China trade issue impact on ASML or others in the equipment business as the administration has kicked that can down the road to congress who will take months to act and probably after Q3 is reported.

    We think ASML remains a core holding in the semiconductor space and perhaps a bit safer haven in the near term memory slow down.

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    Quote Originally Posted by Fred Chen View Post
    With uptime of ~80% per tool, we might estimate the EUV line uptime to be (0.8)^10 ~10-11% but this assumes no correlations among the tool uptimes, which is probably wrong.
    These tools are not in series, they are in parallel. If one of 10 tools is down you have 90% of the throughput. Or if each tool has 80% up time, all ten combined will also have 80% uptime on average.

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    Quote Originally Posted by Staf_Verhaegen View Post
    These tools are not in series, they are in parallel. If one of 10 tools is down you have 90% of the throughput. Or if each tool has 80% up time, all ten combined will also have 80% uptime on average.
    I was considering the specific case of 10 EUV layers, each supported by one tool. The line needs all 10 up.

    The thinking behind it was to have all 10 EUV layer masks of a high volume product loaded on the 10 tools so it would go straight through. Otherwise, you'd have to deal with when to change masks and lots waiting.

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    Quote Originally Posted by Fred Chen View Post
    I was considering the specific case of 10 EUV layers, each supported by one tool. The line needs all 10 up.

    The thinking behind it was to have all 10 EUV layer masks of a high volume product loaded on the 10 tools so it would go straight through. Otherwise, you'd have to deal with when to change masks and lots waiting.
    This is wrong assumption; after litho you have to do etch and other processing steps. The full line is not down when one tool is down; each tool has a queue. EUV tools in one fab are normally matched so one tool can take over from another one if the latter is down.

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    Quote Originally Posted by Staf_Verhaegen View Post
    This is wrong assumption; after litho you have to do etch and other processing steps. The full line is not down when one tool is down; each tool has a queue. EUV tools in one fab are normally matched so one tool can take over from another one if the latter is down.
    Yes, normally there can be more than one available tool that can print the layer, so you can have the backup for that layer. Ideally, it would be nice to support uninterrupted streams. If the tools are all set up for M1 in parallel, when to get to V1?

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    @Fred Chen:
    we might estimate the EUV line uptime to be (0.8)^10 ~10-11% but this assumes no correlations among the tool uptimes, which is probably wrong
    Indeed, that would be valid if you assume EUV downtime is completely random, so all maintenance is unplanned, i.e. curative.

    If it's a line, you'd try to do as much 'planned' as possible.

    Let's say 15% is planned and 5% unplanned, then you'd have uptime of (0,95^10) - 0,15; still pretty lousy ~40% but more than 10%. I wonder what the time needed to change a mask is though... Then you could optimize between line / parallel.

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    Quote Originally Posted by hkwint View Post
    @Fred Chen:


    Indeed, that would be valid if you assume EUV downtime is completely random, so all maintenance is unplanned, i.e. curative.

    If it's a line, you'd try to do as much 'planned' as possible.

    Let's say 15% is planned and 5% unplanned, then you'd have uptime of (0,95^10) - 0,15; still pretty lousy ~40% but more than 10%. I wonder what the time needed to change a mask is though... Then you could optimize between line / parallel.
    Yes, without any particular key product focus, and for flexibility, no reason to have the fixed line. The tools can be independently parallel, and masks changed as needed. Although if there are not enough tools, and some wafers are waiting for one particular product layer (because there's no priority-dedicated tool), their waiting time needs to be accounted for.

    The mask handling is not so trivial, don't want them to get dirty by frequent handling, and also they need to sit in the tool exactly the same way, including on the chuck, to avoid intolerable pattern shifts.

    Also, each tool gets its own mask set, but for the same layer pattern, the treatments may be different on different tools, i.e., different OPC, different SMO, due to aberrations. Worse yet, on the same tool, different positions within the slit may also get different OPC, different SMO. Different SMO actually means different exposures (for that tool).

    With enough tools, such as immersion levels, each product layer could get multiple tool representation, so you can have parallel lines that can be supported.

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    Quote Originally Posted by hkwint View Post
    If it's a line, you'd try to do as much 'planned' as possible.
    The thing is that semiconductor manufacturing is not a line.

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