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Thread: ASML Q1-18 Results: Multiple EUV Orders, 4 High-NA for R&D in 2021 and HVM in 2024

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    ASML Q1-18 Results: Multiple EUV Orders, 4 High-NA for R&D in 2021 and HVM in 2024

    Seems like EUV is marching along quite well as reflected in the presentation of ASML's Q1-18 results, see slide 16 in the presentation material (link below):

    Strong DUV Demand Drives Solid Q1 Results and Confirms Positive Outlook for 2018 - Multiple EUV Orders, Including High-NA, Demonstrate Further Adoption of EUV Technology

    • Q1 net sales of EUR 2.29 billion, net income EUR 540 million, gross margin 48.7 percent
    • ASML expects Q2 2018 net sales between EUR 2.5 billion and EUR 2.6 billion and a gross margin around 43 percent reflecting a significant increase in EUV sales


    Received four orders for High-NA R&D systems from three leading semiconductor manufacturers targeted to start shipping by end of 2021; sold options for eight High-NA early volume systems targeted to start shipping in 2024

    www.asml.com/press/press-releases/strong-duv-demand-drives-solid-q1-results-and-confirms-positive-outlook-for-2018-multiple-euv-orders-including-highna-demonstrate-further-adoption-of-euv-technology/en/s5869?rid=56995

    staticwww.asml.com/doclib/investor/financial_results/2018/asml_20180418_presentation_2018_Q1.pdf

    video presentation by CFO Nickl: asml.corptv.datiq.net/2018Q1_dynZbDcREfMT4Az/video.html

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    Last edited by user nl; 04-17-2018 at 11:02 PM.
     

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    ASML comments from Robert Maire 4/16/2018:

    While its seems somewhat clear to us that ASML has finally gotten most all the major bugs out of their tools we are still not out of the woods. ASML's tools could be functioning flawlessly (which we don't claim they are...) and adoption can still be slow. Why? In a couple of words, infrastructure and experience. The EUV ecosystem is still very immature and a lot of parts are still not ready for prime time. It's also a relatively long list. from resists to reticles and a lot in between. The industry also does not have a lot of experience. From the EDA companies that need to design process and design flow to the tool operators figuring out how to use it. We won't even start to talk about yield management and lack of inspection.....

    It feels as if we are slipping out of a 7NM start and into 5NM. Yes, we are sure that Samsung will push as hard as possible to beat TSMC, but it feels a lot like they may be the "pioneers with arrows in their backs" much like IBM took it on the chin in the 300MM wafer conversion (see ancient history of the semiconductor industry). So while ASML and its tools may be finally on track, we could see a pause as the industry is yet to fully adopt. The focus of the earnings call should change from tool readiness to industry readiness.

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    DAN,

    With all due respect maybe Robert Maire is not the best analyst to refer to regarding the future developments on EUV. This is what Maire said in July 2014 (`someone needs to be taken out to the watershed...`) when IBM announced their first results with the 40 Watt source (www.eetimes.com/document.asp?doc_id=1323296).

    Note how Robert Maire calls the IBM-announcement in 2014 EMPTY NEWS, this was before the days of your president calling facts 'FAKE NEWS' and the reflections of your former FBI director on your president. Somehow Maire reflects to me similar judgement skills and ethics regarding EUV .....:

    ...................
    Investors have yet to figure this out

    The stock was up huge yesterday on the news out of IBM and "confirmed" by ASML about the "watershed" moment in the development of EUV. (someone needs to be taken out to the watershed...)
    We would hope that investors and analysts finally figure out that they have been " had" and ran the stock up on misleading, empty news.
    We would expect that sooner or later even easily fooled investors and analysts will figure this out and the stock will retrace its path.....

    ASML & IBM -Investors Still Don't Get it - What Really Happened

    At that time the ASML stock jumped from around $81 to around $92 (29 to 30 July 2014, see below), almost 4 years later it is around $213 (increase of about 163%).

    And TSMC is finally also ordering the NXE3400 in larger quantities....Apple has perhaps slowed them down somewhat in adopting the EUV tools because of their focus on their annual iPhone cycle upgrades, and less on the medium term developments. And it seems TSMC also ordered now a R&D High-NA tool for delivery in 2021....



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    DateOpenHighLowClose*Adj Close**Volume
    Jul 30, 201492.3096.6791.8295.1492.416,992,400
    Jul 29, 201483.4183.7283.2683.2880.891,190,200
    Jul 28, 201483.9884.7783.5484.4882.061,087,100
    *Close price adjusted for splits.**Adjusted close price adjusted for both dividends and splits.



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    What analyst is the best for EUV? Some people get Robert and some don't. Personally I like him and find his take on things useful.

    In my opinion EUV has been one of the most manipulated topics in semiconductor over the last ten years. I blame ASML as they have EUV duped us all more than once. Robert just posted his take on the ASML call and their "lumpy roll out".






    Quote Originally Posted by user nl View Post
    DAN,

    With all due respect maybe Robert Maire is not the best analyst to refer to regarding the future developments on EUV. This is what Maire said in July 2014 (`someone needs to be taken out to the watershed...`) when IBM announced their first results with the 40 Watt source (www.eetimes.com/document.asp?doc_id=1323296).

    Note how Robert Maire calls the IBM-announcement in 2014 EMPTY NEWS, this was before the days of your president calling facts 'FAKE NEWS' and the reflections of your former FBI director on your president. Somehow Maire reflects to me similar judgement skills and ethics regarding EUV .....:

    ...................
    Investors have yet to figure this out

    The stock was up huge yesterday on the news out of IBM and "confirmed" by ASML about the "watershed" moment in the development of EUV. (someone needs to be taken out to the watershed...)
    We would hope that investors and analysts finally figure out that they have been " had" and ran the stock up on misleading, empty news.
    We would expect that sooner or later even easily fooled investors and analysts will figure this out and the stock will retrace its path.....

    ASML & IBM -Investors Still Don't Get it - What Really Happened

    At that time the ASML stock jumped from around $81 to around $92 (29 to 30 July 2014, see below), almost 4 years later it is around $213 (increase of about 163%).

    And TSMC is finally also ordering the NXE3400 in larger quantities....Apple has perhaps slowed them down somewhat in adopting the EUV tools because of their focus on their annual iPhone cycle upgrades, and less on the medium term developments. And it seems TSMC also ordered now a R&D High-NA tool for delivery in 2021....



    Currency in USD
    Download Data



    |- style="color: rgb(70, 78, 86); font-size: 11px; text-align: right"|- style="border-style: solid; border-width: 1px 0px 0px; border-color: rgb(224, 228, 233); text-align: right; white-space: nowrap"|- style="border-style: solid; border-width: 1px 0px 0px; border-color: rgb(224, 228, 233); color: rgb(70, 78, 86); height: 36px"|-
    |-|-|-|-
    |-|-|-|-
    |-|-|-|-
    DateOpenHighLowClose*Adj Close**Volume
    Jul 30, 201492.3096.6791.8295.1492.416,992,400
    Jul 29, 201483.4183.7283.2683.2880.891,190,200
    Jul 28, 201483.9884.7783.5484.4882.061,087,100
    *Close price adjusted for splits.**Adjusted close price adjusted for both dividends and splits.




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    Quote Originally Posted by Daniel Nenni View Post
    What analyst is the best for EUV? ...................
    My two cents, how about 'your' Scotten? I always like his contributions very much, very fact-like, and he seems to have a good overview of where all EUV tools are located now....I think he has a very good network informing him on the status of process technology at the various leading fabs.

    Scotten seems very respected by the technology minded people, he seems unbiased (no bullying ego problems), just trying to gather and report on the facts as he understands them....

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    I'm not sure Scotten would appreciate being lumped together with "analysts". I consider him to be a technologist guided by logic and the laws of physics and there is no one better in my opinion. On the business side being an analyst is more of an art form. I collaborate with both Scotten and Robert with great pleasure but for very different reasons.


    Quote Originally Posted by user nl View Post
    My two cents, how about 'your' Scotten? I always like his contributions very much, very fact-like, and he seems to have a good overview of where all EUV tools are located now....I think he has a very good network informing him on the status of process technology at the various leading fabs.

    Scotten seems very respected by the technology minded people, he seems unbiased (no bullying ego problems), just trying to gather and report on the facts as he understands them....

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    A number of EUV issues have come to light, which, while not necessarily being showstoppers, will be troublesome to deal with, just from metrology alone. The most obvious ones currently are aberrations and stochastics. Aberrations will require specific metrology monitor vehicles in real time, as the optics gets heated up. ASML had something called FlexWave for DUV but not EUV; it could add flare and absorption and reduce throughput. Stochastics is now known to be manifest as missing or bridging features, will need inspection of over 10 billion features in one die, not just millions. A lot of time will need to be spent on baseline data collection alone.

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    Last edited by Fred Chen; 04-20-2018 at 09:17 AM. Reason: FlexWave for DUV not EUV
     

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    INTEL on EUV

    For quite some time INTEL said some like `we are going to use EUV when it is ready`. It seems that in their Q1-18 call they finally publicly said that EUV is ready for them to use. In response to some questions on the 10 nm ramp push out due to yield issues they seem to admit that they were a little too aggressive in setting their 10 nm shrink goals, all with DUV multi-patterning and not a single layer of EUV lithography by INTEL in their 10 nm node (yet?):

    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Brian M. Krzanich - Intel Corp.
    Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.
    And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.
    So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.
    As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.
    And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers.

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    Quote Originally Posted by user nl View Post
    For quite some time INTEL said some like `we are going to use EUV when it is ready`. It seems that in their Q1-18 call they finally publicly said that EUV is ready for them to use. In response to some questions on the 10 nm ramp push out due to yield issues they seem to admit that they were a little too aggressive in setting their 10 nm shrink goals, all with DUV multi-patterning and not a single layer of EUV lithography by INTEL in their 10 nm node (yet?):

    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Brian M. Krzanich - Intel Corp.
    Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.
    And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.
    So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.
    As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.
    And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers.
    I don't see any confidence in EUV at all. You'd figure, with more confidence in EUV, they could increase above 2.7 rather than back off to 2.4. Also they're not skipping 10nm to EUV 7nm in 2019, but continuing to improve the multipatterning yield of 10nm.

    What's strange in their presentation though is that the CEO referred to as much as six-pass patterning, which is excessive given they reported using SAQP at IEDM. The minimum pitch is 36 nm for the M1 direction, and 40 nm for M0 and 44 nm for M2. so four masks should be sufficient. Although they had an M0 layer with 40 nm pitch, where they decided to go SAQP instead of SADP. That seems counterintuitive for helping yield. TSMC and Globalfoundries were using SADP at that pitch.

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    INTEL on EUV part2

    I am no semi-technology expert, and perhaps Scotten (or others) likes to chip in his 2-cents (or more) here. In another reply INTEL seem to hint at 'upgraded' versions of the 10 nm technology. Could those include some EUV layers, as a practice before moving to full EUV 7 nm?
    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Timothy Arcuri - UBS Securities LLC

    Thank you. I actually had a two-part question on 10-nano. The issues seemed to be going on now for some time, and it's almost as if the design libraries or something are flawed. So I guess the first question is why not skip 10-nanometer and go directly to 7-nanometer? You guys have a lot of EUV experience and it's going to cut out a lot of the multi-pattern layers. So that's the first question.
    And number two, the real question is that if you did that, would that be a net drag to gross margin looking out because you never really monetized 10-nanometer? Thanks.
    Brian M. Krzanich - Intel Corp.
    Okay, so let me try and answer your question. No, there's nothing wrong with the design libraries or anything like that. The proof of that is that we're shipping product. So if there were basic functionality issues like that, you wouldn't be able to produce and ship the product. Again, as I said, this is all around how many layers are on multi-patterning and the end of life of the immersion for the critical layers.
    The second part of your question was would it benefit to just skip to 7 nanometers, and would that have an effect on the capital or the gross margins? The simple answer is no. I don't think that's a good idea. The best answer is there's a lot of learning that will happen that we can carry forward into 7 nanometers just like we carried from 14-nanometer to 10-nanometer.
    The other thing is that we still hold – roughly 80% of our capital equipment is fungible to the next node or backwards to the prior node. And so that's why as we've shifted 10-nanometer and 14-nanometer, we were able to do that without shifting our capital expenditures greatly from – we're able to just move the capacity back and forth. The same thing is going to happen between 10-nanometer and 7-nanometer. So you'll have some percentage, and it's always based on demand and how fast things are ramping and all of that. But the equipment will be fungible for the most part between 10-nanometer and 7-nanometer as well.
    But no, the right thing to do is exactly what we're doing. This is a unique opportunity we have. There's a lot more performance than 14-nanometer. We can keep driving that. We'll fix the yield issues. If 10-nanometer can have a 10-nanometer, a 10-plus, a 10-plus-plus, you're going to see a lot of products and a lot of performance out of that technology.

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    Quote Originally Posted by user nl View Post
    I am no semi-technology expert, and perhaps Scotten (or others) likes to chip in his 2-cents (or more) here. In another reply INTEL seem to hint at 'upgraded' versions on the 10 nm technology. Could those include some EUV layers, as a practice before moving to full EUV 7 nm?
    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Timothy Arcuri - UBS Securities LLC

    Thank you. I actually had a two-part question on 10-nano. The issues seemed to be going on now for some time, and it's almost as if the design libraries or something are flawed. So I guess the first question is why not skip 10-nanometer and go directly to 7-nanometer? You guys have a lot of EUV experience and it's going to cut out a lot of the multi-pattern layers. So that's the first question.
    And number two, the real question is that if you did that, would that be a net drag to gross margin looking out because you never really monetized 10-nanometer? Thanks.
    Brian M. Krzanich - Intel Corp.
    Okay, so let me try and answer your question. No, there's nothing wrong with the design libraries or anything like that. The proof of that is that we're shipping product. So if there were basic functionality issues like that, you wouldn't be able to produce and ship the product. Again, as I said, this is all around how many layers are on multi-patterning and the end of life of the immersion for the critical layers.
    The second part of your question was would it benefit to just skip to 7 nanometers, and would that have an effect on the capital or the gross margins? The simple answer is no. I don't think that's a good idea. The best answer is there's a lot of learning that will happen that we can carry forward into 7 nanometers just like we carried from 14-nanometer to 10-nanometer.
    The other thing is that we still hold – roughly 80% of our capital equipment is fungible to the next node or backwards to the prior node. And so that's why as we've shifted 10-nanometer and 14-nanometer, we were able to do that without shifting our capital expenditures greatly from – we're able to just move the capacity back and forth. The same thing is going to happen between 10-nanometer and 7-nanometer. So you'll have some percentage, and it's always based on demand and how fast things are ramping and all of that. But the equipment will be fungible for the most part between 10-nanometer and 7-nanometer as well.
    But no, the right thing to do is exactly what we're doing. This is a unique opportunity we have. There's a lot more performance than 14-nanometer. We can keep driving that. We'll fix the yield issues. If 10-nanometer can have a 10-nanometer, a 10-plus, a 10-plus-plus, you're going to see a lot of products and a lot of performance out of that technology.
    It implies most equipment common between 14nm, 10nm, and 7nm so they were able to shift around, so I doubt 7nm would be mostly EUV.

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    INTEL and 10nm++

    I guess I'm really slow in catching up on INTEL's 10++ technology, David Schor has reported on this already some months ago, reporting how INTEL (Turkot) disclosed already in Feb 2018 at IEDM 2017 + ISSCC 2018 the following:

    ---------------------------------------------------------------
    All in all, Intel is confident that EUV is on a solid path to HVM insertion, however Turkot was careful to note that insertion will only take place when the technology is ready and cost effective. We believe Intel will insert EUV in late 2019/early 2020 in preparation for their “10nm++” 3rd generation enhanced process.

    IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects – Page 7 – WikiChip Fuse

    David Schor – WikiChip Fuse
    -----------------------------------------------------------------

    Maybe with the push-out of 10 nm to 2019 EUV is finally both ready AND cost-effective for INTEL

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    Quote Originally Posted by user nl View Post
    I guess I'm really slow in catching up on INTEL's 10++ technology, David Schor has reported on this already some months ago, reporting how INTEL (Turkot) disclosed already in Feb 2018 at IEDM 2017 + ISSCC 2018 the following:

    ---------------------------------------------------------------
    All in all, Intel is confident that EUV is on a solid path to HVM insertion, however Turkot was careful to note that insertion will only take place when the technology is ready and cost effective. We believe Intel will insert EUV in late 2019/early 2020 in preparation for their “10nm++” 3rd generation enhanced process.

    IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects – Page 7 – WikiChip Fuse

    David Schor – WikiChip Fuse
    -----------------------------------------------------------------

    Maybe with the push-out of 10 nm to 2019 EUV is finally both ready AND cost-effective for INTEL
    The pattern has always been new EUV problems emerge to push it out further.

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    Yield issues and inspection

    I noticed that there is quite some discussion on the eetimes website as to the origin of the INTEL 10 nm yield issues and volume production delay to 2019. Some commentators (IanD ?) seem to doubt the edge placement issues mention by INTEL's CEO and suggest that Cobalt is the origin of the slow 10 nm yield ramping:

    https://www.eetimes.com/document.asp...d=1333230#msgs


    It seems the high-throughput high-resolution full wafer inspection, while ramping, is getting more and more important at these advanced 10/7 nm nodes.

    Below an interesting recent story on the state-of-the-art inspection tools being developed, especially also the (multi) e-beam technology:
    Semiconductor Engineering .:. E-beam Inspection Makes Inroads

    Now I also understand better the somewhat cryptic comment by ASML's (leaving) CFO Wolfgang Nickl at Q1-2018 investor call on his prediction that inspection tools were becoming a huge market for ASML:
    ASML Holding's (ASML) CEO Peter Wennink on Q1 2018 Results - Earnings Call Transcript | Seeking Alpha

    For some time already ASML was predicting that their Hermes-ebeam business would contribute 1 BEuro revenue in 2020!

    Let's see if ASML/Hermes can ramp up their multi-ebeam inspection tools, in combination with their holistic computational approach, and the (high-NA)-EUV/DUV lithography, to a fast expanding node-monopoly litho-company for the 10/7/5 and beyond advanced nodes.

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    Last edited by user nl; 04-29-2018 at 01:21 AM.
     

  16. #16
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    It appears to me that recent news favours those who went with EUV and is against those who stayed away from EUV. The report is that Samsung 7nm R&D is done and they are shifting focust to 5nm. They are ahead of schedule by about 3 months on that. TSMC will do 7nm+ soon, and results are better than expected as well. Intel, on the other hand, has been saying "EUV is not ready... EUV is not ready", and now have a 2019 release (perhaps) after horrible delays. To me, that shows Intel has lost its way by losing appetite for risk. In this case, those who risked appear to be gaining the most. EUV is ready, and no technology has ever been without a shortcoming or two, if perfection was the requirement for success, nothing would ever have made it. Fortunately, the debate is moot, Intel will now begin losing money due to their shortsightedness.

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    Quote Originally Posted by DrizztVD View Post
    It appears to me that recent news favours those who went with EUV and is against those who stayed away from EUV. The report is that Samsung 7nm R&D is done and they are shifting focust to 5nm. They are ahead of schedule by about 3 months on that. TSMC will do 7nm+ soon, and results are better than expected as well. Intel, on the other hand, has been saying "EUV is not ready... EUV is not ready", and now have a 2019 release (perhaps) after horrible delays. To me, that shows Intel has lost its way by losing appetite for risk. In this case, those who risked appear to be gaining the most. EUV is ready, and no technology has ever been without a shortcoming or two, if perfection was the requirement for success, nothing would ever have made it. Fortunately, the debate is moot, Intel will now begin losing money due to their shortsightedness.
    If Samsung were so confident in EUV, there would have been no reason for them to release 8nm with quadruple patterning.

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  18. #18
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    SMIC / China orders latest EUV NXE3400 tool from ASML

    TAIPEI -- Semiconductor Manufacturing International Co., China's top state-backed contract chipmaker, has placed an order for one set of extreme-ultraviolet lithography equipment, the costliest and most advanced chip production tool, to close technology gaps with market leaders and to secure the supply of critical gear amid trade tensions between the U.S. and China, according to people familiar with the matter.

    The company's move to purchase its first EUV lithography equipment from Dutch chip gear builder ASML, worth $120 million, highlights its growing ambition to help boost Chinese homegrown semiconductor manufacturing technology, even though it is still two to three generations behind market leaders. The move also secures the supply of the cutting-edge lithography tool that all top global chip giants, including Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing Co., are buying to ensure the later production of more powerful and advanced chips.

    TSMC, Intel and Samsung have already ordered many EUV systems from ASML. TSMC, the world's biggest contract chipmaker by revenue, for instance, has booked up to 10 systems for this year, according to supply chain sources. Samsung has booked roughly six EUV systems, while Intel will take about three for 2018, these people said.

    GlobalFoundries, the world's No. 2 contract chipmaker, also placed an order for one. ASML said in a mid-April earnings call that it plans to ship 20 EUV systems in 2018, without specifying customers' orders.

    The order by SMIC in April came after the U.S. said it will ban Chinese telecommunications equipment maker ZTE from using American-made components and services for seven years, said an industry source familiar with the situation.
    Chinese chipmaker takes on TSMC and Intel with cutting-edge tool -
    Nikkei Asian Review

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  19. #19
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    Quote Originally Posted by user nl View Post
    TAIPEI -- Semiconductor Manufacturing International Co., China's top state-backed contract chipmaker, has placed an order for one set of extreme-ultraviolet lithography equipment, the costliest and most advanced chip production tool, to close technology gaps with market leaders and to secure the supply of critical gear amid trade tensions between the U.S. and China, according to people familiar with the matter.

    The company's move to purchase its first EUV lithography equipment from Dutch chip gear builder ASML, worth $120 million, highlights its growing ambition to help boost Chinese homegrown semiconductor manufacturing technology, even though it is still two to three generations behind market leaders. The move also secures the supply of the cutting-edge lithography tool that all top global chip giants, including Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing Co., are buying to ensure the later production of more powerful and advanced chips.

    TSMC, Intel and Samsung have already ordered many EUV systems from ASML. TSMC, the world's biggest contract chipmaker by revenue, for instance, has booked up to 10 systems for this year, according to supply chain sources. Samsung has booked roughly six EUV systems, while Intel will take about three for 2018, these people said.

    GlobalFoundries, the world's No. 2 contract chipmaker, also placed an order for one. ASML said in a mid-April earnings call that it plans to ship 20 EUV systems in 2018, without specifying customers' orders.

    The order by SMIC in April came after the U.S. said it will ban Chinese telecommunications equipment maker ZTE from using American-made components and services for seven years, said an industry source familiar with the situation.
    Chinese chipmaker takes on TSMC and Intel with cutting-edge tool -
    Nikkei Asian Review
    It's an intriguing report. Not sure if Wassenaar has any teeth anymore. Perhaps 7nm development seems a harmless enough purpose.

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  20. #20
    DrizztVD
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    Quote Originally Posted by Fred Chen View Post
    If Samsung were so confident in EUV, there would have been no reason for them to release 8nm with quadruple patterning.
    Your statement is simply not logical. There is no correlation between being confident in EUV and doing 8nm. 8nm is useful in maxing out quadruple patterning feature reduction, it allows earlier introduction with high-volume tools since EUV is supply constrained and thus there is not enough EUV equipment available for a direct jump to 7nm within the same timeframe.

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