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Thread: ASML Q1-18 Results: Multiple EUV Orders, 4 High-NA for R&D in 2021 and HVM in 2024

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    ASML Q1-18 Results: Multiple EUV Orders, 4 High-NA for R&D in 2021 and HVM in 2024

    Seems like EUV is marching along quite well as reflected in the presentation of ASML's Q1-18 results, see slide 16 in the presentation material (link below):

    Strong DUV Demand Drives Solid Q1 Results and Confirms Positive Outlook for 2018 - Multiple EUV Orders, Including High-NA, Demonstrate Further Adoption of EUV Technology

    • Q1 net sales of EUR 2.29 billion, net income EUR 540 million, gross margin 48.7 percent
    • ASML expects Q2 2018 net sales between EUR 2.5 billion and EUR 2.6 billion and a gross margin around 43 percent reflecting a significant increase in EUV sales


    Received four orders for High-NA R&D systems from three leading semiconductor manufacturers targeted to start shipping by end of 2021; sold options for eight High-NA early volume systems targeted to start shipping in 2024

    www.asml.com/press/press-releases/strong-duv-demand-drives-solid-q1-results-and-confirms-positive-outlook-for-2018-multiple-euv-orders-including-highna-demonstrate-further-adoption-of-euv-technology/en/s5869?rid=56995

    staticwww.asml.com/doclib/investor/financial_results/2018/asml_20180418_presentation_2018_Q1.pdf

    video presentation by CFO Nickl: asml.corptv.datiq.net/2018Q1_dynZbDcREfMT4Az/video.html

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    Last edited by user nl; 4 Weeks Ago at 11:02 PM.
     

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    ASML comments from Robert Maire 4/16/2018:

    While its seems somewhat clear to us that ASML has finally gotten most all the major bugs out of their tools we are still not out of the woods. ASML's tools could be functioning flawlessly (which we don't claim they are...) and adoption can still be slow. Why? In a couple of words, infrastructure and experience. The EUV ecosystem is still very immature and a lot of parts are still not ready for prime time. It's also a relatively long list. from resists to reticles and a lot in between. The industry also does not have a lot of experience. From the EDA companies that need to design process and design flow to the tool operators figuring out how to use it. We won't even start to talk about yield management and lack of inspection.....

    It feels as if we are slipping out of a 7NM start and into 5NM. Yes, we are sure that Samsung will push as hard as possible to beat TSMC, but it feels a lot like they may be the "pioneers with arrows in their backs" much like IBM took it on the chin in the 300MM wafer conversion (see ancient history of the semiconductor industry). So while ASML and its tools may be finally on track, we could see a pause as the industry is yet to fully adopt. The focus of the earnings call should change from tool readiness to industry readiness.

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    DAN,

    With all due respect maybe Robert Maire is not the best analyst to refer to regarding the future developments on EUV. This is what Maire said in July 2014 (`someone needs to be taken out to the watershed...`) when IBM announced their first results with the 40 Watt source (www.eetimes.com/document.asp?doc_id=1323296).

    Note how Robert Maire calls the IBM-announcement in 2014 EMPTY NEWS, this was before the days of your president calling facts 'FAKE NEWS' and the reflections of your former FBI director on your president. Somehow Maire reflects to me similar judgement skills and ethics regarding EUV .....:

    ...................
    Investors have yet to figure this out

    The stock was up huge yesterday on the news out of IBM and "confirmed" by ASML about the "watershed" moment in the development of EUV. (someone needs to be taken out to the watershed...)
    We would hope that investors and analysts finally figure out that they have been " had" and ran the stock up on misleading, empty news.
    We would expect that sooner or later even easily fooled investors and analysts will figure this out and the stock will retrace its path.....

    ASML & IBM -Investors Still Don't Get it - What Really Happened

    At that time the ASML stock jumped from around $81 to around $92 (29 to 30 July 2014, see below), almost 4 years later it is around $213 (increase of about 163%).

    And TSMC is finally also ordering the NXE3400 in larger quantities....Apple has perhaps slowed them down somewhat in adopting the EUV tools because of their focus on their annual iPhone cycle upgrades, and less on the medium term developments. And it seems TSMC also ordered now a R&D High-NA tool for delivery in 2021....



    Currency in USD
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    |- style="color: rgb(70, 78, 86); font-size: 11px; text-align: right"|- style="border-style: solid; border-width: 1px 0px 0px; border-color: rgb(224, 228, 233); text-align: right; white-space: nowrap"|- style="border-style: solid; border-width: 1px 0px 0px; border-color: rgb(224, 228, 233); color: rgb(70, 78, 86); height: 36px"|-
    |-|-|-|-
    |-|-|-|-
    DateOpenHighLowClose*Adj Close**Volume
    Jul 30, 201492.3096.6791.8295.1492.416,992,400
    Jul 29, 201483.4183.7283.2683.2880.891,190,200
    Jul 28, 201483.9884.7783.5484.4882.061,087,100
    *Close price adjusted for splits.**Adjusted close price adjusted for both dividends and splits.



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    What analyst is the best for EUV? Some people get Robert and some don't. Personally I like him and find his take on things useful.

    In my opinion EUV has been one of the most manipulated topics in semiconductor over the last ten years. I blame ASML as they have EUV duped us all more than once. Robert just posted his take on the ASML call and their "lumpy roll out".






    Quote Originally Posted by user nl View Post
    DAN,

    With all due respect maybe Robert Maire is not the best analyst to refer to regarding the future developments on EUV. This is what Maire said in July 2014 (`someone needs to be taken out to the watershed...`) when IBM announced their first results with the 40 Watt source (www.eetimes.com/document.asp?doc_id=1323296).

    Note how Robert Maire calls the IBM-announcement in 2014 EMPTY NEWS, this was before the days of your president calling facts 'FAKE NEWS' and the reflections of your former FBI director on your president. Somehow Maire reflects to me similar judgement skills and ethics regarding EUV .....:

    ...................
    Investors have yet to figure this out

    The stock was up huge yesterday on the news out of IBM and "confirmed" by ASML about the "watershed" moment in the development of EUV. (someone needs to be taken out to the watershed...)
    We would hope that investors and analysts finally figure out that they have been " had" and ran the stock up on misleading, empty news.
    We would expect that sooner or later even easily fooled investors and analysts will figure this out and the stock will retrace its path.....

    ASML & IBM -Investors Still Don't Get it - What Really Happened

    At that time the ASML stock jumped from around $81 to around $92 (29 to 30 July 2014, see below), almost 4 years later it is around $213 (increase of about 163%).

    And TSMC is finally also ordering the NXE3400 in larger quantities....Apple has perhaps slowed them down somewhat in adopting the EUV tools because of their focus on their annual iPhone cycle upgrades, and less on the medium term developments. And it seems TSMC also ordered now a R&D High-NA tool for delivery in 2021....



    Currency in USD
    Download Data



    |- style="color: rgb(70, 78, 86); font-size: 11px; text-align: right"|- style="border-style: solid; border-width: 1px 0px 0px; border-color: rgb(224, 228, 233); text-align: right; white-space: nowrap"|- style="border-style: solid; border-width: 1px 0px 0px; border-color: rgb(224, 228, 233); color: rgb(70, 78, 86); height: 36px"|-
    |-|-|-|-
    |-|-|-|-
    |-|-|-|-
    DateOpenHighLowClose*Adj Close**Volume
    Jul 30, 201492.3096.6791.8295.1492.416,992,400
    Jul 29, 201483.4183.7283.2683.2880.891,190,200
    Jul 28, 201483.9884.7783.5484.4882.061,087,100
    *Close price adjusted for splits.**Adjusted close price adjusted for both dividends and splits.




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    Quote Originally Posted by Daniel Nenni View Post
    What analyst is the best for EUV? ...................
    My two cents, how about 'your' Scotten? I always like his contributions very much, very fact-like, and he seems to have a good overview of where all EUV tools are located now....I think he has a very good network informing him on the status of process technology at the various leading fabs.

    Scotten seems very respected by the technology minded people, he seems unbiased (no bullying ego problems), just trying to gather and report on the facts as he understands them....

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    I'm not sure Scotten would appreciate being lumped together with "analysts". I consider him to be a technologist guided by logic and the laws of physics and there is no one better in my opinion. On the business side being an analyst is more of an art form. I collaborate with both Scotten and Robert with great pleasure but for very different reasons.


    Quote Originally Posted by user nl View Post
    My two cents, how about 'your' Scotten? I always like his contributions very much, very fact-like, and he seems to have a good overview of where all EUV tools are located now....I think he has a very good network informing him on the status of process technology at the various leading fabs.

    Scotten seems very respected by the technology minded people, he seems unbiased (no bullying ego problems), just trying to gather and report on the facts as he understands them....

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    A number of EUV issues have come to light, which, while not necessarily being showstoppers, will be troublesome to deal with, just from metrology alone. The most obvious ones currently are aberrations and stochastics. Aberrations will require specific metrology monitor vehicles in real time, as the optics gets heated up. ASML had something called FlexWave for DUV but not EUV; it could add flare and absorption and reduce throughput. Stochastics is now known to be manifest as missing or bridging features, will need inspection of over 10 billion features in one die, not just millions. A lot of time will need to be spent on baseline data collection alone.

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    INTEL on EUV

    For quite some time INTEL said some like `we are going to use EUV when it is ready`. It seems that in their Q1-18 call they finally publicly said that EUV is ready for them to use. In response to some questions on the 10 nm ramp push out due to yield issues they seem to admit that they were a little too aggressive in setting their 10 nm shrink goals, all with DUV multi-patterning and not a single layer of EUV lithography by INTEL in their 10 nm node (yet?):

    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Brian M. Krzanich - Intel Corp.
    Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.
    And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.
    So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.
    As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.
    And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers.

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    Quote Originally Posted by user nl View Post
    For quite some time INTEL said some like `we are going to use EUV when it is ready`. It seems that in their Q1-18 call they finally publicly said that EUV is ready for them to use. In response to some questions on the 10 nm ramp push out due to yield issues they seem to admit that they were a little too aggressive in setting their 10 nm shrink goals, all with DUV multi-patterning and not a single layer of EUV lithography by INTEL in their 10 nm node (yet?):

    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Brian M. Krzanich - Intel Corp.
    Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.
    And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.
    So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.
    As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.
    And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers.
    I don't see any confidence in EUV at all. You'd figure, with more confidence in EUV, they could increase above 2.7 rather than back off to 2.4. Also they're not skipping 10nm to EUV 7nm in 2019, but continuing to improve the multipatterning yield of 10nm.

    What's strange in their presentation though is that the CEO referred to as much as six-pass patterning, which is excessive given they reported using SAQP at IEDM. The minimum pitch is 36 nm for the M1 direction, and 40 nm for M0 and 44 nm for M2. so four masks should be sufficient. Although they had an M0 layer with 40 nm pitch, where they decided to go SAQP instead of SADP. That seems counterintuitive for helping yield. TSMC and Globalfoundries were using SADP at that pitch.

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