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Thread: ASML Q1-18 Results: Multiple EUV Orders, 4 High-NA for R&D in 2021 and HVM in 2024

  1. #11
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    INTEL on EUV part2

    I am no semi-technology expert, and perhaps Scotten (or others) likes to chip in his 2-cents (or more) here. In another reply INTEL seem to hint at 'upgraded' versions of the 10 nm technology. Could those include some EUV layers, as a practice before moving to full EUV 7 nm?
    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Timothy Arcuri - UBS Securities LLC

    Thank you. I actually had a two-part question on 10-nano. The issues seemed to be going on now for some time, and it's almost as if the design libraries or something are flawed. So I guess the first question is why not skip 10-nanometer and go directly to 7-nanometer? You guys have a lot of EUV experience and it's going to cut out a lot of the multi-pattern layers. So that's the first question.
    And number two, the real question is that if you did that, would that be a net drag to gross margin looking out because you never really monetized 10-nanometer? Thanks.
    Brian M. Krzanich - Intel Corp.
    Okay, so let me try and answer your question. No, there's nothing wrong with the design libraries or anything like that. The proof of that is that we're shipping product. So if there were basic functionality issues like that, you wouldn't be able to produce and ship the product. Again, as I said, this is all around how many layers are on multi-patterning and the end of life of the immersion for the critical layers.
    The second part of your question was would it benefit to just skip to 7 nanometers, and would that have an effect on the capital or the gross margins? The simple answer is no. I don't think that's a good idea. The best answer is there's a lot of learning that will happen that we can carry forward into 7 nanometers just like we carried from 14-nanometer to 10-nanometer.
    The other thing is that we still hold – roughly 80% of our capital equipment is fungible to the next node or backwards to the prior node. And so that's why as we've shifted 10-nanometer and 14-nanometer, we were able to do that without shifting our capital expenditures greatly from – we're able to just move the capacity back and forth. The same thing is going to happen between 10-nanometer and 7-nanometer. So you'll have some percentage, and it's always based on demand and how fast things are ramping and all of that. But the equipment will be fungible for the most part between 10-nanometer and 7-nanometer as well.
    But no, the right thing to do is exactly what we're doing. This is a unique opportunity we have. There's a lot more performance than 14-nanometer. We can keep driving that. We'll fix the yield issues. If 10-nanometer can have a 10-nanometer, a 10-plus, a 10-plus-plus, you're going to see a lot of products and a lot of performance out of that technology.

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    Last edited by user nl; 4 Weeks Ago at 10:36 PM.
     

  2. #12
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    Quote Originally Posted by user nl View Post
    I am no semi-technology expert, and perhaps Scotten (or others) likes to chip in his 2-cents (or more) here. In another reply INTEL seem to hint at 'upgraded' versions on the 10 nm technology. Could those include some EUV layers, as a practice before moving to full EUV 7 nm?
    Intel (INTC) Q1 2018 Results - Earnings Call Transcript | Seeking Alpha


    Timothy Arcuri - UBS Securities LLC

    Thank you. I actually had a two-part question on 10-nano. The issues seemed to be going on now for some time, and it's almost as if the design libraries or something are flawed. So I guess the first question is why not skip 10-nanometer and go directly to 7-nanometer? You guys have a lot of EUV experience and it's going to cut out a lot of the multi-pattern layers. So that's the first question.
    And number two, the real question is that if you did that, would that be a net drag to gross margin looking out because you never really monetized 10-nanometer? Thanks.
    Brian M. Krzanich - Intel Corp.
    Okay, so let me try and answer your question. No, there's nothing wrong with the design libraries or anything like that. The proof of that is that we're shipping product. So if there were basic functionality issues like that, you wouldn't be able to produce and ship the product. Again, as I said, this is all around how many layers are on multi-patterning and the end of life of the immersion for the critical layers.
    The second part of your question was would it benefit to just skip to 7 nanometers, and would that have an effect on the capital or the gross margins? The simple answer is no. I don't think that's a good idea. The best answer is there's a lot of learning that will happen that we can carry forward into 7 nanometers just like we carried from 14-nanometer to 10-nanometer.
    The other thing is that we still hold – roughly 80% of our capital equipment is fungible to the next node or backwards to the prior node. And so that's why as we've shifted 10-nanometer and 14-nanometer, we were able to do that without shifting our capital expenditures greatly from – we're able to just move the capacity back and forth. The same thing is going to happen between 10-nanometer and 7-nanometer. So you'll have some percentage, and it's always based on demand and how fast things are ramping and all of that. But the equipment will be fungible for the most part between 10-nanometer and 7-nanometer as well.
    But no, the right thing to do is exactly what we're doing. This is a unique opportunity we have. There's a lot more performance than 14-nanometer. We can keep driving that. We'll fix the yield issues. If 10-nanometer can have a 10-nanometer, a 10-plus, a 10-plus-plus, you're going to see a lot of products and a lot of performance out of that technology.
    It implies most equipment common between 14nm, 10nm, and 7nm so they were able to shift around, so I doubt 7nm would be mostly EUV.

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  3. #13
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    INTEL and 10nm++

    I guess I'm really slow in catching up on INTEL's 10++ technology, David Schor has reported on this already some months ago, reporting how INTEL (Turkot) disclosed already in Feb 2018 at IEDM 2017 + ISSCC 2018 the following:

    ---------------------------------------------------------------
    All in all, Intel is confident that EUV is on a solid path to HVM insertion, however Turkot was careful to note that insertion will only take place when the technology is ready and cost effective. We believe Intel will insert EUV in late 2019/early 2020 in preparation for their “10nm++” 3rd generation enhanced process.

    IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects – Page 7 – WikiChip Fuse

    David Schor – WikiChip Fuse
    -----------------------------------------------------------------

    Maybe with the push-out of 10 nm to 2019 EUV is finally both ready AND cost-effective for INTEL

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  4. #14
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    Quote Originally Posted by user nl View Post
    I guess I'm really slow in catching up on INTEL's 10++ technology, David Schor has reported on this already some months ago, reporting how INTEL (Turkot) disclosed already in Feb 2018 at IEDM 2017 + ISSCC 2018 the following:

    ---------------------------------------------------------------
    All in all, Intel is confident that EUV is on a solid path to HVM insertion, however Turkot was careful to note that insertion will only take place when the technology is ready and cost effective. We believe Intel will insert EUV in late 2019/early 2020 in preparation for their “10nm++” 3rd generation enhanced process.

    IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects – Page 7 – WikiChip Fuse

    David Schor – WikiChip Fuse
    -----------------------------------------------------------------

    Maybe with the push-out of 10 nm to 2019 EUV is finally both ready AND cost-effective for INTEL
    The pattern has always been new EUV problems emerge to push it out further.

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    Yield issues and inspection

    I noticed that there is quite some discussion on the eetimes website as to the origin of the INTEL 10 nm yield issues and volume production delay to 2019. Some commentators (IanD ?) seem to doubt the edge placement issues mention by INTEL's CEO and suggest that Cobalt is the origin of the slow 10 nm yield ramping:

    https://www.eetimes.com/document.asp...d=1333230#msgs


    It seems the high-throughput high-resolution full wafer inspection, while ramping, is getting more and more important at these advanced 10/7 nm nodes.

    Below an interesting recent story on the state-of-the-art inspection tools being developed, especially also the (multi) e-beam technology:
    Semiconductor Engineering .:. E-beam Inspection Makes Inroads

    Now I also understand better the somewhat cryptic comment by ASML's (leaving) CFO Wolfgang Nickl at Q1-2018 investor call on his prediction that inspection tools were becoming a huge market for ASML:
    ASML Holding's (ASML) CEO Peter Wennink on Q1 2018 Results - Earnings Call Transcript | Seeking Alpha

    For some time already ASML was predicting that their Hermes-ebeam business would contribute 1 BEuro revenue in 2020!

    Let's see if ASML/Hermes can ramp up their multi-ebeam inspection tools, in combination with their holistic computational approach, and the (high-NA)-EUV/DUV lithography, to a fast expanding node-monopoly litho-company for the 10/7/5 and beyond advanced nodes.

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    It appears to me that recent news favours those who went with EUV and is against those who stayed away from EUV. The report is that Samsung 7nm R&D is done and they are shifting focust to 5nm. They are ahead of schedule by about 3 months on that. TSMC will do 7nm+ soon, and results are better than expected as well. Intel, on the other hand, has been saying "EUV is not ready... EUV is not ready", and now have a 2019 release (perhaps) after horrible delays. To me, that shows Intel has lost its way by losing appetite for risk. In this case, those who risked appear to be gaining the most. EUV is ready, and no technology has ever been without a shortcoming or two, if perfection was the requirement for success, nothing would ever have made it. Fortunately, the debate is moot, Intel will now begin losing money due to their shortsightedness.

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  7. #17
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    Quote Originally Posted by DrizztVD View Post
    It appears to me that recent news favours those who went with EUV and is against those who stayed away from EUV. The report is that Samsung 7nm R&D is done and they are shifting focust to 5nm. They are ahead of schedule by about 3 months on that. TSMC will do 7nm+ soon, and results are better than expected as well. Intel, on the other hand, has been saying "EUV is not ready... EUV is not ready", and now have a 2019 release (perhaps) after horrible delays. To me, that shows Intel has lost its way by losing appetite for risk. In this case, those who risked appear to be gaining the most. EUV is ready, and no technology has ever been without a shortcoming or two, if perfection was the requirement for success, nothing would ever have made it. Fortunately, the debate is moot, Intel will now begin losing money due to their shortsightedness.
    If Samsung were so confident in EUV, there would have been no reason for them to release 8nm with quadruple patterning.

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    SMIC / China orders latest EUV NXE3400 tool from ASML

    TAIPEI -- Semiconductor Manufacturing International Co., China's top state-backed contract chipmaker, has placed an order for one set of extreme-ultraviolet lithography equipment, the costliest and most advanced chip production tool, to close technology gaps with market leaders and to secure the supply of critical gear amid trade tensions between the U.S. and China, according to people familiar with the matter.

    The company's move to purchase its first EUV lithography equipment from Dutch chip gear builder ASML, worth $120 million, highlights its growing ambition to help boost Chinese homegrown semiconductor manufacturing technology, even though it is still two to three generations behind market leaders. The move also secures the supply of the cutting-edge lithography tool that all top global chip giants, including Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing Co., are buying to ensure the later production of more powerful and advanced chips.

    TSMC, Intel and Samsung have already ordered many EUV systems from ASML. TSMC, the world's biggest contract chipmaker by revenue, for instance, has booked up to 10 systems for this year, according to supply chain sources. Samsung has booked roughly six EUV systems, while Intel will take about three for 2018, these people said.

    GlobalFoundries, the world's No. 2 contract chipmaker, also placed an order for one. ASML said in a mid-April earnings call that it plans to ship 20 EUV systems in 2018, without specifying customers' orders.

    The order by SMIC in April came after the U.S. said it will ban Chinese telecommunications equipment maker ZTE from using American-made components and services for seven years, said an industry source familiar with the situation.
    Chinese chipmaker takes on TSMC and Intel with cutting-edge tool -
    Nikkei Asian Review

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  9. #19
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    Quote Originally Posted by user nl View Post
    TAIPEI -- Semiconductor Manufacturing International Co., China's top state-backed contract chipmaker, has placed an order for one set of extreme-ultraviolet lithography equipment, the costliest and most advanced chip production tool, to close technology gaps with market leaders and to secure the supply of critical gear amid trade tensions between the U.S. and China, according to people familiar with the matter.

    The company's move to purchase its first EUV lithography equipment from Dutch chip gear builder ASML, worth $120 million, highlights its growing ambition to help boost Chinese homegrown semiconductor manufacturing technology, even though it is still two to three generations behind market leaders. The move also secures the supply of the cutting-edge lithography tool that all top global chip giants, including Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing Co., are buying to ensure the later production of more powerful and advanced chips.

    TSMC, Intel and Samsung have already ordered many EUV systems from ASML. TSMC, the world's biggest contract chipmaker by revenue, for instance, has booked up to 10 systems for this year, according to supply chain sources. Samsung has booked roughly six EUV systems, while Intel will take about three for 2018, these people said.

    GlobalFoundries, the world's No. 2 contract chipmaker, also placed an order for one. ASML said in a mid-April earnings call that it plans to ship 20 EUV systems in 2018, without specifying customers' orders.

    The order by SMIC in April came after the U.S. said it will ban Chinese telecommunications equipment maker ZTE from using American-made components and services for seven years, said an industry source familiar with the situation.
    Chinese chipmaker takes on TSMC and Intel with cutting-edge tool -
    Nikkei Asian Review
    It's an intriguing report. Not sure if Wassenaar has any teeth anymore. Perhaps 7nm development seems a harmless enough purpose.

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  10. #20
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    Quote Originally Posted by Fred Chen View Post
    If Samsung were so confident in EUV, there would have been no reason for them to release 8nm with quadruple patterning.
    Your statement is simply not logical. There is no correlation between being confident in EUV and doing 8nm. 8nm is useful in maxing out quadruple patterning feature reduction, it allows earlier introduction with high-volume tools since EUV is supply constrained and thus there is not enough EUV equipment available for a direct jump to 7nm within the same timeframe.

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