In order to continue innovating and succeeding, design engineers need a trusted resource for information and analysis that helps them make the correct technology decisions. The Tech Design Forum provides this resource, bringing together EDA industry experts, the EE design community and solution providers to collectively address the hottest issues, trends and products that affect the EDA industry. This is accomplished via both a quarterly Journal and worldwide free events. Network with your peers and gain critical information in a FREE, one-day conference that includes:


  • Industry experts discussing the latest design issues and trends
  • In-depth technical sessions focusing on critical design challenges and practical solutions you can put to use immediately
  • Vendor fair with eco system solution providers demonstrating new products


With multiple stops worldwide, the Tech Design Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies. It provides an excellent opportunity for EE designers and engineers to network with their peers and, conversely, for EDA solution providers to reach those markets.
Tech Design Forum 2011 Wiki-eda-tech-forum-history.jpg

Videos from Tech Design Forum Santa Clara 2011:


DFM State of the Art at 28nm
Design-for-Manufacturing comprises a broad range of tools and methodologies to minimize systematic defects and improve both functional and parametric yield. The importance and challenge of DFM increases at each technology node, and techniques are continuously evolving, industry experts from all parts of the ecosystem will discuss DFM requirements, methods, tooling and experiences at 28nm. Essentially this will be a quick primer on what designers need to prepare for at advanced nodes.

DRC+ State of the art at 28nm
GLOBALFOUNDRIES’ proprietary Library of Yield Detractors Patterns and their innovative DRC+ physical verification flow are now implemented on Mentor’s Calibre® platform, which in addition to equation-based verification and comprehensive DFM, now includes pattern matching-based design rule checking capabilities for mutual customers, with support for GUI-based pattern creation and library management enabling custom rule development.

Yield Analysis State of the art at 28nm

Delivering a correct, high yielding product on time becomes more and more difficult at each node due to the increasing potential for systematic, design specific defects. This session shows how to increase IC yield using statistical analysis of volume test diagnosis data in a way that augments traditional solutions. The methodology, which relies on accurate single-die diagnosis of scan test failures, gives engineers a proven, very fast, and highly effective new way of defect localization and identification. This approach can also be the foundation for a collaborative process between fabless and foundry customers, benefiting both sides..

Enabling the Collaboration Across the Ecosystem to Deliver Maximum Innovation
At advanced nodes manufacturing success is highly sensitive to specific physical design features, requiring more complex design rules and more attention to manufacturability on the part of designers. Experts will discuss how collaboration among EDA vendors, IP suppliers, foundries and design firms is the key to enabling efficient design without over-constraining and limiting designers' creativity. The discussion will touch on what has been accomplished, including industry initiatives under way, and where we need to go in the future.

Is 3D a Real Option Today?
While Moore's Law may be alive and well, it's certainly not cheap! Is the cost of IC scaling reaching a point of diminishing returns? With new 3D scaling alternatives such as Through Silicon Vias (TSV), does it make more sense to "go vertical" like real estate in Manhattan? This panel will host a discussion on the key issues surrounding 3D multi-die packaging, which affects everything from system design through IC implementation and testing. As 3D IC evolves over the next five years, what are the economic, performance, and power tradeoffs? Are we really ready for TSV in production? How will it affect the design, verification and testing flows? Plus many more questions that attends are sure to pose to the panelists.



Speakers and Panel Moderators

  • Rob Aitken, ARM Fellow, ARM
  • Simon Burke, Distinguished Engineer, Xilinx
  • Luigi Capodieci, R&D Fellow, DFM CAD, GLOBALFOUNDRIES
  • Vito Dai, Ph.D., DRC+ Principal Architect, GLOBALFOUNDRIES
  • Paul Dempsey, Editor-In-Chief, EDA Tech Forum Journal
  • Renaud Gelin, Principle IC Design Engineer, Broadcom
  • Rich Goldman, Vice President Corporate Marketing & Strategic Alliances, Synopsys
  • Thomas Herrmann, MTS Product Engineer, Yield Analysis Systems, GLOBALFOUNDRIES
  • Vishal Kapoor, VP Corporate Relationship Marketing, Cadence
  • Hao Lee, Senior Principal Design Engineer, Broadcom
  • Kuang-Kuo Lin, Ph.D., Director, Foundry Design Enablement, Samsung
  • Ashok B. Mehta, Senior Manager (DTP/SJDMP), TSMC
  • Rich Morse, Technical Marketing Manager, SpringSoft
  • Bernard Murphy, CTO, Atrenta
  • John Murphy, Director of Strategic Alliances Marketing, Cadence
  • Daniel Nenni, Blogger, SemiWiki.com
  • Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES
  • Dave Pietromonaco, Principal Engineer, ARM
  • Tom Quan, Deputy Director of Design Methodology & Service Marketing, TSMC
  • Mark Redford, VP U.S. Operations, Cambridge Silicon Radio
  • Norma Rodriguez, Senior Member Technical Staff, AMD
  • Prasad Subramaniam, VP of R&D and Design Technology, eSilicon
  • Ron Wilson, Editorial Director, EDN and DesignLines, UBM Electronics