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Thread: SPICE and FastSPICE Vendors Wiki

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    Blogger Daniel Payne's Avatar
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    Post SPICE and FastSPICE Vendors Wiki

    Before SPICE
    In 1967 a circuit simulation program called BIAS was developed by Howard [1], followed by CANCER from Nagel while in a research group of Rohrer.

    SPICE
    Professor Pederson's class created SPICE (Simulation Program with Integrated Circuit Emphasis) in 1971 to simulate the timing and power of ICs, then released SPICE publicly in 1972. The original versions of SPICE are available from Berkeley under a BSD licence that allows for modification and sale (without having to share the source), so many companies have used at as the base of a simulator. Newer simulators and "fast" SPICE simulators may use different internals but read the same netlists (for which there is no official standard).

    Introduction


    Circuit designers typically use a schematic capture tool to enter their design at the transistor-level, create a netlist, then simulate the design in SPICE and visualize the voltage and current waveforms with a viewer.

    Analysis

    Engineers run multiple analysis simulations to answer questions about the performance of their design versus the specification that they are trying to meet or exceed:
    • DC (Direct Current)
    • AC (Alternating Current)
    • Transient
    • Monte Carlo
    • Sensitivity
    • Noise
    • Reliability
    • Harmonic balance
    • Periodic steady state
    • Optimization
    • ERC (Electrical Rule Check)

    EDA Vendors

    Here's a list of EDA vendors offering SPICE, and FastSPICE circuit simulators. Let me know if I missed any and I'll update the post.

    SPICE

    ToolCompanyInputsAnalysisComments
    ADS Transient ConvolutionAgilent EEsof EDASchematic, ADS, SPICE, Spectre, HSPICE, Verilog-ADC, Transient, AC, noise (Harmonic balance and circuit envelope options)Device models (BSIM, etc.). DES encryption. Integration with frequency domain (via causal convolution) and distributed transmission line elements (multi layer models library, Momentum multilayer 3DEM, FEM abitrary geometry 3DEM). Schematic capture. Data display. Traditional IBIS. Time-domain (bit-by-bit) and statistical channel simulators with eye diagram and IBIS AMI flow. Jitter decomposition. Broadband SPICE model generator. Measurement hardened.
    HSPICESynopsysHSPICE, Verilog-ADC, Transient, AC, Frequency, MC, MOSRA, ACMatch, DCMatch, RF (HSPICE RF), loop stability, transient noiseDevice models (BSIM, PSP, HiSIM, HVMOS, TFT, etc.). Triple DES encryption. Integration with Synopsys Custom Designer, Custom Waveview. Integration with Cadence Virtuoso Analog Design Environment (ADE). W-element. Statistical eye diagram (with IBIS AMI).
    Spectre Circuit SimulatorCadenceSpectre, SPICE, Verilog-A 2.0, S-parameter data filesDC, Transient, AC, Frequency, MC, noise, transfer function, sensitviity, transient noise, reliability, harmonic balance, periodic and quasi-periodic steady state, periodic and quasi-periodic small signal, time domain and frequency domain envelope, RF with turboanalog, RF, mixed-signal, integrated with Virtuoso custom design platform, co-simulation with Simulink. Webinar blog, November 2011.
    PSpiceCadenceOrCAD, Allegro Design Entry-HDLDC, Transient, AC, MC, Smoke, temperature, stress, sensitivity, optimizerPower supplies, high-frequency, simple IC designs, integrated with OrCAD Capture, MATLAB Simulink for co-simulation, PCB flow integration
    Spectre Accelerated Parallel SimulatorCadenceSpectre, SPICE, Verilog-A, S-parameter data filesDC, Transient, AC, transient noise, relibility, MC, RF harmonic balance, RF shooting Newton, RF FAST envelope, RF noise and small signalscalable multi-core simulation, analog and RF designs. Webinar blog, November 2011.
    Eldo ClassicMentorEldo, HSPICE, Verilog-A, SpectreDC, Transient, AC, Noise, transfer function, loop stability, incremental
    Monte Carlo, Safe Opeating Area analysis, Hi-Z checks, transient noise, DC mismatch, aging, AC, DC sensitivity, AC sensitivity, transient sensitivity, aging sensitivity, pole-zero analysis, large signal multi-tone steady-state analysis, phase noise, non-linear contribution analysis, modulated steady-state analysis
    Scalable multi-threading, integrated with Mentor and Cadence frameworks, up to 1M devices, RLCCK parasitic reduction, DSPF backannotation, distributed to multi-cpus (LSF, Grid and proprietary dispatchers), built-in optimization, bisection, waveform outputs (.wdb, .tr0, .psf, .fsdb), analog and digital macro models, all standard models (BSIM3, BSIM4, PSP, HiSIM, HiSIM/HV, EKV, HICUM, VBIC, MEXTRAM, BSIMSOI, TFT), IBIS 5.0, S-parameters, microstrip models, lossy and lossless transmission lines, API for proprietary model integration, optional netlist case-sensitivity, integrated with Questa-AMS for mixed-signal verification
    FineSim SPICESynopsysHSPICE, Spectre, EldoDC, transient, AC, MCMulti-cpu. Outputs (FineWave, tr0, fsdb, wdf). Integrated with SiliconSmart library characterization products. Acquired from Magma.
    RASERInfinisim
    SmartSpiceSilvaco
    T-SpiceTanner EDAHSPICE, PSpiceDC, transient, AC, MCMulti-threaded. Model support: PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, RPI a-Si & Poly-Si TFT, BMIC, MEXTRAM.
    MSIMLegend DesignSPICE, Verilog-ADC, transient, AC, MCMulti-threaded, multi-core. TSMC certified. Built-in RC reduction. Model support (BSIM3, BSIM4, HiSim, TFT, BJT, diode, RPI, s-parameter, IBIS, etc.). Outputs: wdf, fsdb, tr0, ascii.
    ACCITACCIT New Systems ResearchGPU powered.
    NgspiceOpen Source
    QucsOpen SourceGUI and schematics
    SIMetrix SPICESIMetrixPSPICE, HSPICE,
    Verilog-A,
    Verilog-HDL
    DC, transient, real time noise, AC, MC, Nyquist, FFTAlso SIMPLIS for PLL, switching, complex modulation simulation. Schematic capture, graphing capability, scripting language, parallel support (multi-CPU).
    XSpiceAltiumbundled inside of Altium Designer, PCB focus.
    IsSpice4Intusoft
    CoolSpiceCoolCAD ElectronicsDC, transient, AC. Model support (in free student version): MOS1 (level 1), MOS2 (level 2), MOS3 (level 3), BSIM1 (level 4), BSIM2 (level 5), MOS6 (level 6), MOS7 (level 7), BSIM3 (level 8/49) (3.0=3.0, 3.1=3.1, 3.2=3.2.4, 3.3=3.3.0), MOS9 (level 9), BSIM4 (level 4/54) (4.0=4.2.1, 4.1=4.2.1, 4.2=4.2.1, 4.3=4.3.0, 4.4=4.4.0, 4.5=4.5.0, 4.6=4.6.2), B3SOIFD (level 55), B3SOIDD (level 56), B3SOIPD (level 57), B4SOI (level 10/58), SOI3 (level 60). Cryogenic CMOS models and high-temp.-high-power silicon carbide (SiC) device models in the commercial version. Commercial version supports 3D-thermal-electrical simulations for SiC devices.
    LTspice IVLinear TechnologyFocus on switching regulators, includes schematics and waveform viewer.
    NI MultisimNational InstrumentsPart of Electronics Workbench.
    TINA ProDesignWare IncPCB layout, schematics, simulation.
    NexximAnsyssimulator inside of Designer, SI and RF simulation focus.
    SymSpiceSYMICAHSPICE, Spectre, Verilog-ADC, AC, Transient, Sweep, MCStart-up from San Jose (V1.02, April 2011). HiSIM HV models. Schematic capture (Q1 2012). Open Access support (Q3 2014).
    NanoDesignerProplusSpin-out from Cadence/Celestry in 2007
    Micro-CapSpectrum SoftwareIntegrated schematic editor and SPICE simulator, founded in 1980
    5Spice5SpicePSpiceDC, AC, TransientDiscrete level simulation with schematics and waveform viewing. Free download with restricted features.







    Historic SPICE Simulators

    ToolCompanyInputsAnalysisComments
    Syscap
    ECAPIBMUsed in the 1960s.
    BELAC



    Analog FastSPICE

    ToolCompanyInputsAnalysisComments
    Spectre XPSCadenceSpectre, SPICE, HSPICEDC, TransientAnnounced on October 9, 2013. Capacity of ten's of millions of devices. About 10X faster than Spectre APS. Aimed at embedded memory and IR drop analysis use.
    Analog FastSPICE PlatformBerkeley Design AutomationSPICE (HSPICE and Spectre netlist and simulator options); DSPF; Verilog-ADC, transient, AC, pole/zero, S-parameter analysis, .NET multiport, stability analysis, small signal transfer function (tf/xf), noise analysis.

    AFS Co-sim option (HDL co-simulation with Verilog).

    AFS Transient Noise option (transient noise analysis).

    AFS RF option (pss, pnoise, pstb, pac, pxf, oscpss/oscnoise, vcopss/vconoise analyses); Harmonic Balance (hbpss, hbnoise, hbpac, hbpxf analyses).
    >10M element capacity; accuracy from nanometer SPICE to near SPICE; multithreaded for single simulation runs and MultiCore Parallel (MCP) for repeated runs (Monte Carlo, sweeps, alter, etc); WaveCrave and CalcPad viewing and post-processing. AFS Nano (same core simulator, capacity 5k elements).

    Fully integrated into Cadence's ADE.

    Model support includes BSIM3, BSIM4, BSIMSOI, PSP, MOS1/3, MOS9, MOS11, Mextram, HICUM, HiSIM_HV, VBIC, JFET, diode, juncap, BJT, Gummel-Poon, physical resistor, fracpole, tline, S-parameter, W-element.

    Netlist and model encryption.
    PCSIMCyberedaSPICEDC, transientParallel, multi-cpu, million device capacity, model support (BSIM3, BSIM4, BJT, diode), viewer support (nWave - SpringSoft, anaWave - AnaGlobe, Berkeley Nutmeg)
    Eldo PremierMentorEldo, HSPICE, Spectre, Verilog-ADC, Transient, incremental Monte Carlo, Aging, Safe Operating Area10M devices capacity, 2.5x to 20x faster than Eldo Classic with identical accuracy, native multi-threading, integrated with Mentor and Cadence frameworks, RLCCK parasitic reduction, DSPF backannotation, distributed to multi-cpus (LSF, Grid and proprietary dispatchers), built-in optimization, bisection, waveform outputs (.wdb, .tr0, .psf, .fsdb), analog and digital macro models, all standard models (BSIM3, BSIM4, PSP, HiSIM, HiSIM/HV, EKV, HICUM, VBIC, MEXTRAM, BSIMSOI, TFT), S-parameters, microstrip models, lossy and lossless transmission lines, API for proprietary model integration, optional netlist case-sensitivity, integrated with Questa-AMS for mixed-signal verification






    Analog but not based on Berkeley SPICE

    ToolCompanyInputsAnalysisComments
    GnucapOpen SourceSPICE compatible

    FastSPICE

    ToolCompanyInputsAnalysisComments
    HSIMSynopsysHSPICE, Verilog-A, Spectre, Eldo, VCD, parasitics (DPF, SPEF, DSPF)AC, DC, transient, MC, FFTHierarchical, built-in RCC reduction, integrated with Cadence Virtuoso, XA option (new engine)
    NanoSIMSynopsysSPICE, HSPICE, Verilog, EDIF, LSIM, parasitics (SPF, SPEF)AC, DC, transient, interactive, function checks, power analysis, timing analysismodel support (BJT, BSIM3, BSIM4, MM905, JFET, MESFET, HVMOS, SiGe VBIC, SOI), Cadence integration, TurboWave integration, co-simulation with Verilog (VCS), XA option (new engine)
    CustomSimSynopsysHSPICE, Spectre, Eldo, Verilog-A, parasitics (SPF, DPF, SPEF), VCDAC, DC, transient, MC, interactive, function checks, power analysis, timing analysisCombined: HSIM, NanoSim, XA. Tcl scripting. Outputs (WDF, WDB, FSDB, etc.). Models (HSPICE, Spectre, Eldo).
    Virtuoso UltraSimCadenceSPICE, Spectre, Veilog-A, DSPF, SPEF, Verilog-AMS, VHDL-AMS, Verilog, VHDL, PLI, SystemC, SystemVerilogERC, Power, Timing, Node ActivityHierarchical, integrated with Virtuoso Layout. In maintenance mode after announcement of Spectre XPS in October 2013.
    ADiTMentorEldo, HSPICE, Spectre, Verilog-A, parasitics (DSPF, SPF), VCDDC, transient, MC, reliability (aging), Hi-Z and leakage10 million device capacity, Outputs (.wdb, .fsdb, ADit, .tr0, .tb0), integrated with Cadence Virtuoso, waveform (EZwave), RC reduction, mixed-signal simulation with Questa ADMS, save/restart
    FineSim PROSynopsysHSPICE, Spectre, Eldo, parasitics (DSPF)DC, transient, AC, MC, EM (option)From Magma, now Synopsys. Multi-CPU. Models (electrically exact, BSIM3, BSIM4, BSIM-SOI, Phillips MM9, Gummel-Poon, VBIC 1.2, Philips Mextram 503, Diode, RLC, inverted inductance). Outputs (.tr0, fsdb, wdf). Co-simulation (Verilog, VHDL). RC reduction. SiliconSmart library characterization integration.
    Turbo MSIMLegend DesignSPICE, HSPICEDC, transient, AC, MCHierarchical. Built-in RC reduction. Device models (BSIM3, BSIM4, BJT, diode). Outputs (wdf, fsdb, ascii).



    References

    1. From nano to space: applied mathematics inspired by Roland Bulirsch By Roland Bulirsch, Michael H. Breitner, Georg Denk, Peter Rentrop

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    SPICE equivalents?

    Thank you! It is great to have an ongoing listing.
    It would be even more useful if the list could be annotated (be people more knowledgeable than I) to indicate specific characteristics.
    For example, whether simulators using different algorithms could be expected always to be at least as accurate as standard SPICE.
    There are at least two reasons this may not be the case: convergence algorithms and specific approximations; for example:
    For transients, PSPICE uses the Gear2 algorithm exclusively. Although it is an option in standard SPICE, it is usually reserved for specific purposes because it makes circuits appear better damped than they actually are.
    Similarly, some of the simulators use extended local linear approximations to accelerate the simulation.
    Other simulators accelerate the simulations by handling reactive components in the Laplace domain. Quicker and more accurate whenever component "Q's allow.
    Then there are simulators that use enhanced matrix algorithms - sometimes primarily for acceleration, but the consequences could include increased accuracy. (Then again, LTSPICE has an optional matrix algorithm that gives enhanced accuracy but runs slower than with its standard settings).

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    George,
    You're right, by adding more info the list becomes more valuable. I'm thinking about using a table format with info like:
    Inputs, Outputs, Types of Analysis, Frequency Range

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    Hi Daniel, You have transient analysis and noise analysis separate. I think it's becoming important now to add "transient noise analysis". I haven't kept up in the last year or two, but Berkeley Design Automation's transient noise engine is awesome.
    Posted by Glenn Crosby

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    SPICE is good for some tasks and some types of circuits, but the readily available SPICE models do not encompass all the parasitic elements in a typical part and its external/internal factors. That is why a testboard and/or prototype must be made and tested on the bench to flush out all of those issues. As Bob Pease used to say "In theory, practice and theory should be the same. In practice, they are not."
    Posted by Bill McCulley

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    Quote Originally Posted by admin View Post
    the readily available SPICE models do not encompass all the parasitic elements in a typical part and its external/internal factors. "
    Posted by Bill McCulley
    I think this (or comprehensive measurement of parts) can be critical for using predesigned components where fully detailed models are unavailable. However, for IC design:
    In most (not all) respects post-layout extractions of the better PDKs align better with reality than any single process run aligns with any other [they use multi-component models to overcome some of your issues]. Similarly, the data for packages are either reasonable as provided or can be modelled or extracted. Similarly PCB analysis tools.
    At this point the most significant limitations on final simulation appear to be the substrate parasitics (diode series resistance) and the complex substrate interactions - and unfortunately the latter may well require that the "prototype" is a complete circuit. The comparison then needs to be between the circuit and the simulation at the same process point (and if you are not careful, even this can be clouded by the effects of mismatches).
    Then there is the issue that even the best kits do not make a decent attempt at substrate parasitics at the pre-layout stage. Indeed, for me the biggest reduction in "churn" would be to support a larger measure of layout definition and parasitic estimation in the preliminary schematics (rather than to require layouts from the first stage for the subcircuits that are individually back-extracted before any sensible evaluation of parasitics can be made)
    What breadboards are really "best" at is enforcing critical questions that the designer forgot to ask of the simulator.
    [I can't remember Pease's exact wording, but he gave the example of Widlar (who only ever designed analytically) when stating that it came down to a question of the designer's skills]

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    Last edited by George Storm; 05-19-2011 at 03:59 AM. Reason: Clarification
     

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    Quote Originally Posted by admin View Post
    Hi Daniel, You have transient analysis and noise analysis separate. I think it's becoming important now to add "transient noise analysis". I haven't kept up in the last year or two, but Berkeley Design Automation's transient noise engine is awesome.
    Posted by Glenn Crosby
    Agreed: transient noise analysis (otherwise called "real time noise" is a great tool. In (subject to correction) approximate order of implementation (earliest first), SIMetrix, (Eldo, SmartSpice & Spectre, HSPICE, TSpice and FineSim also provide this capability. [I've probably missed some] The pain of course lies in the simulation time required to obtain statistically valid results, and in the post-simulation analyses.
    [Perhaps it's preferable to use quasi-steady-state simulators in the situations where they can provide the the information you need]

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    I find all too often engineers will enter simplistic circuits with perfect reactances with no loss and then wonder why they get no convergence, (infinite dv/dt and di/dt ?).
    Well they wont find perfect components in the real world so why expect them in a SPICE circuit

    Also SPICE models are based on typical performance. No one offers worse case models and in aerospace you have to do a formal worse case analysis with minimal available data. Its a nightmare .
    Posted by Alan Bate

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    Fast-Spice simulators are ok if you want to develop a wall switch or jumper cables for your old car but they are unsuitable for real design consistent with eDFM requirements in the nanoscale era.
    Posted by Robert Pack

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    Quote Originally Posted by admin View Post
    Fast-Spice simulators are ok if you want to develop a wall switch or jumper cables for your old car but they are unsuitable for real design consistent with eDFM requirements in the nanoscale era.
    Posted by Robert Pack
    We obviously don't need fast-spice for the wall-switch or jumper-cables.
    Are you saying that there is no market for (non-analogue) FastSpice.
    Or that final simulations (the longest ones) cannot rely on these tools?

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    There have been developments by several EDA vendors that have greatly increased speed to the Fast-Spice level, some, like BDA, have done that with Analog FastSPICE without loss of accuracy compared to Spectre or HSPICE. Full Disclosure - I worked at BDA as an apps guy a few years back. Cadence was doing pretty well with their APS engine as well.
    Posted by Glenn Crosby

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    Perhaps these might be of interest for addition to the table & list:
    Simulator: Saber, the first and in some sense still the best table-based circuit simulator, which I have used extensively for analog chip design and big co-sim jobs in Hspice model environment, via the 'new Spice to Saber' translater NSpiToS.
    Analysis: time domain noise, pole-zero, worst case, successive injection, symbolic; Virtuoso Analog Design Environment lists 26 analysis types.
    Eldo analysis types, is a listing wanted (table has blank areas)? Eldo does most everything Hspice does, but better, in my considered judgement, including analysis types, I used it full time for 4 years next to Hspice. Far fewer bugs.

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    There are several of the lower cost spice simulators missing and one with incorrect info.

    First of all Tina is made and sold by Designsoft: DesignSoft main page. Pretty capable mixed-signal product with VHDL support. Latest version is multithreaded to take full advantage of multiple core processors. Probably the easiest to use and get up to speed on.

    Missing products:


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    Last edited by mfortunato; 12-26-2012 at 01:01 PM.
     

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