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Thread: Semiconductor IP Outsourcing Wiki

  1. #1
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    Semiconductor IP Outsourcing Wiki

    According to trusted sources it costs upwards of $50M to design a 40nm ASIC down to the GDS. Semiconductor IP is a growing part of that equation but even in the never ending quest for optimum semiconductor unit cost per function, the semiconductor IP make-versus-buy decision is often overlooked. The numbers I have heard are downwards of 30% of IP that can be outsourced is outsourced.

    Semiconductor IP Outsourcing  Wiki-soc-costs.jpg


    There are a number of considerations that determine the feasibility of commercial semiconductor IP. It’s a standard Make vs Buy decision based on cost and delivery. The Buy cost of the IP should not exceed the Make cost otherwise the trend to develop IP internally will continue. Royalty or success based back-end pricing models simplifies this equation quite a bit. You also have to factor in the Not Invented Here (NIH) syndrome which is a powerful force of nature in the semiconductor industry.

    Semiconductor IP Outsourcing  Wiki-ip-roi.jpg


    If a company does have the required experience and market window to develop the IP, the commercial IP value proposition is much more difficult. If you do choose to Make the IP however, you also need to estimate the risk of additional costs and lost profits due to IP related delays. That risk increases significantly with each new process node and exploding transistor count. The Global Semiconductor Alliance (GSA) has a handy Semi IP ROI calculator for just this purpose which looks at IP qualitative, IP quantitative, product ROI baseline, product development expense, product marketing introduction, and product market share metrics.


    Semiconductor IP Outsourcing  Wiki-market-delay-inputs.jpg

    Three messages from this spreadsheet:

    1. If two or more vendors can supply the IP you require, it probably is better to purchase rather than make. Choosing a vendor that has good quality and will stand by their IP is critical. Notice, I did not state vendor IP customization. Any IP changes destroy any value added from the vendor’s validation and compliance testing. You basically start from square one.

    2. With multiple IP vendors available, development teams should focus on key items that allow them to differentiate their product in the market place. Internally developing a standards based interface (i.e. USB) is wasting valuable resources that could be applied elsewhere.

    3. If we remove the quality of IP (yes, there are potential quality issues in purchased OR internally developed IP), being late to market and losing potential market share/early premium pricing is MUCH larger loss than overspending on either your internal engineering team OR in the purchase price of IP. The often referred to IBS study shows the impact of being late to market. Many books will show sensitivity to various development expenses vs. revenue impact. I believe this portion of the ROI Calculator was removed in the second revision.


    Semiconductor IP Outsourcing  Wiki-ip-roi.jpg


    If you choose the right IP vendor (forget the price!), the development time AND risk are lowered. Various SW tools are still required but they focus on either converting (i.e. C/C++ to RTL to gates, netlist to routed GDSII) or analyzing (simulation, STA, DRC/LVS/ERC, etc). Tools had a huge positive impact on resources required to complete a design and has lowered the risk. I cannot imagine going back to 1970s and designing chips using those ‘old’ methods. I consider SW tools as the 1st generation ‘technology’ that we continue to expand as new methods or phenomenon require new tools to support. Once a tool is adopted, each release has improved functionality and QoR. IP (whether IP or silicon fabric) is the second generation and it continues to evolve from primitive gates, to megacells to sub-systems to known good die (KGD) for 3D ICs.

    For most “standards-based” design IP, commercial IP companies amortize the Make cost of IP development and set a Buy price proportionally less than the total NRE it takes to Make it so cost is rarely a gating issue in today’s market conditions. In the case of the physical layer or Hard IP this is definitely the case. Some semiconductor companies will look to their internal Analog and Mixed Signal (AMS) development expertise as a market differentiator for their end product. However, with the exploding demand for AMS designs, experienced AMS teams are in great demand which makes joint development partnerships, subcontracting, or complete Hard IP outsourcing even more attractive.

    Nevertheless, the NIH syndrome remains a strong force so the pressure to develop IP internally is real. An alternate strategy would be to establish a Joint Development Partnership (JDP) with commercial IP companies. This requires an “open ecosystem” mindset by management that correlates the market demand and the capabilities of the two partners. The mitigated risk of a JDP with an established commercial IP provider allows for even more efficiency and cost reductions on both parts. So prepare for a new force of nature in semiconductor design and manufacture, the PFE or Proudly Found Elsewhere Syndrome.

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    IP ROI Calculator

    Daniel,
    Glad you found the IP ROI Calculator useful. From your write up, it seems you are working with the first generation that I created for GSA. A second version that removed some of the complexity was recently released.
    NIH is a huge issue as well as underestimating the internal costs to develop, validate, compliance test, document, support and maintain IP. This underestimating might be ‘unconscious NIH’ as the Excel spreadsheet is filled in.
    Three of the messages from this spreadsheet:
    1. If two or more vendors can supply the IP you require, it probably is better to purchase rather than make. Choosing a vendor that has good quality and will stand by their IP is critical. Notice, I did not state vendor IP customization. Any IP changes destroy any value added from the vendor’s validation and compliance testing. You basically start from square one.
    2. With multiple IP vendors available, development teams should focus on key items that allow them to differentiate their product in the market place. Internally developing a standards based interface (i.e. USB) is wasting valuable resources that could be applied elsewhere.
    3. If we remove the quality of IP (yes, there are potential quality issues in purchased OR internally developed IP), being late to market and losing potential market share/early premium pricing is MUCH larger loss than overspending on either your internal engineering team OR in the purchase price of IP. The often referred to IBS study shows the impact of being late to market. Many books will show sensitivity to various development expenses vs. revenue impact. I believe this portion of the ROI Calculator was removed in the second revision.
    If you choose the right IP vendor (forget the price!), the development time AND risk are lowered. Various SW tools are still required but they focus on either converting (i.e. C/C++ to RTL to gates, netlist to routed GDSII) or analyzing (simulation, STA, DRC/LVS/ERC, etc). Tools had a huge positive impact on resources required to complete a design and has lowered the risk. I cannot imagine going back to 1970s and designing chips using those ‘old’ methods. I consider SW tools as the 1st generation ‘technology’ that we continue to expand as new methods or phenomenon require new tools to support. Once a tool is adopted, each release has improved functionality and QoR. IP (whether IP or silicon fabric) is the second generation and it continues to evolve from primitive gates, to megacells to sub-systems to known good die (KGD) for 3D ICs.
    I am pleased to see is that IP is finally being understood as the potential 10x-100x accelerator in product development. EricE’s reports show high CAGR in various IP sectors, higher than many other EDA areas.
    Bill

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    perhaps the low percentage of IP out sourced is simply a reflection of the problems involved. common problems include : negotitiating a deal may take a lot of time and effert, most IP has to be checked and modified before use in any case, your supplier may have incomptible procedures, tools and a different agenda and of course if your chip includes other peoples IP you are at risk of losing control of the project. from my experience when you go external your costs / risk etc increase by 20% or more, but these costs ar never anticipated by managers before the project begins.
    Posted by David James

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    I think in few years all standard based interface will be procured as IP by SoC companies unless the interface is a critical differentiator for the SoC. The interface standards are changing very rapidly and to incorporate those new features dedicated focus is needed. For a small and medium SoC company it is a quite challenging task. A company with special focus on a standard can easily accomodate that.

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