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Thread: Interface IP: PCI Express Wiki

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    Blogger Eric Esteve's Avatar
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    Interface IP: PCI Express Wiki

    PCI Express (PCIe) standard protocol was initially developed by Intel. The PCI Special Interest Group (PCI-SIG) is in charge of issuing PCIe specification, organizing the compliance workshop (Plug fest), maintaining the list of compliant products and so on.

    Interface IP: PCI Express Wiki-pcie-ip-part.jpg

    PCIe is a differential serial, dual simplex, point to point protocol, supporting links which are scalable, offering x1, x4, x8, x16 or x32 width. The transfer rate will depend on the Base specification:
    • Base 1.0 or Gen-1 is defined at 2.5 Gbps; this gives a bandwidth of 2.0 Gb/s (8b/10b encoding) per lane, so for example a PCIe Gen-1 x8 link deliver an aggregate bandwidth of 2 GB/s
    • Base 2.0 or Gen-2 is defined at 5 Gbps; this gives a bandwidth of 4.0 Gb/s (8b/10b encoding) per lane, so for example a PCIe Gen-2 x16 link deliver an aggregate bandwidth of 8 GB/s
    • Base 2.0 or Gen-3 is defined at 8 Gbps; this gives a bandwidth of 8.0 Gb/s (Scrambling + 128b/130b encoding instead of 8b/10b encoding) per lane, so for example a PCIe Gen-3 x8 link deliver an aggregate bandwidth of 8 GB/s
    The protocol is backward compatible. At initialization, auto-negotiation procedure allows the two agents to stick with the highest common rate, so you can plug an End Point Gen-1 to a Root Port Gen-3, the link will run at 2.5 Gigatransfer per second per lane.

    PCIe has been developed as the PC motherboard interconnects (between CPU and GPU for example) and can also be used to interface with daughter boards, through a PCIe connector. The success of PCIe in the PC segment has pushed for a wide adoption in the embedded segments. Most of the processor recently launched support PCIe Interface, as well as do the FPGA from Altera, Lattice, Xilinx since 2005. A few ASSP vendors are selling PCIe based products, from Clock buffer or Bridges, to complex PCIe switches: PLX, IDT (Tundra acquisition), Gennum… This leads to give some explanation about the PCIe “topology”.

    When the PCIe function is located at the Host, it is called the Root Port (RP). You can either attach to the RP directly a peripheral device, with a PCIe End Point function (EP), or a Switch, in this case the Root is called Root Complex (RC). The Switch will be made of one Upstream link (attached to the RP), the switching function and a number of Downstream links. To these links you will attach several EP, located on several peripheral devices. So, by topology we mean one of these functions: RP, RC, EP, SW-UP or SW-DN. You can also find bridge, the more popular were the PCIe to PCI bridges, allowing to keep using a legacy system with PCIe.

    Interface IP: PCI Express Wiki-04f3a91924d5fc2b37fa4166.jpg

    The standard define a real communication layered protocol (Physical, Data Link, Transaction, and Application layers), with features like various size payloads, virtual channels (one logical link can support up to 8 VC).

    PCI-SIG has issued specification for more complex usage of PCI Express, targeted to the high end PC segments (servers), probably too much specific to attract customers from the embedded market:
    “PCI-SIG I/O Virtualization (IOV) Specifications, in conjunction with system virtualization technologies, allow multiple operating systems running simultaneously within a single computer to natively share PCI Express® devices. These specifications are grouped into three areas:
    ·Address Translation Services (ATS): this specification provides a set of transactions for PCI Express components to exchange and use translated addresses in support of native I/O Virtualization.
    ·Single Root IOV: this specification provides native I/O Virtualization in existing PCI Express topologies where there is a single root complex.
    ·Multi-Root IOV: this specification builds on the Single Root IOV Specification to provide native I/O Virtualization in new topologies (such as blade servers) where multiple root complexes share a PCI Express hierarchy.”
    If we look at the PCIe market, we can see it is massively used in PC (no surprise), in embedded PC and for Communication Boards.

    Interface IP: PCI Express Wiki-board-market.jpg
    The IP solution is mostly used in the Embedded, Communication and PC peripheral segments; in fact, the PC segment (Chipset and GPU) is massively using internally developed solution, considering PCIe as a strategic feature. As a specific market, the PCIe IP has seen a strong growth (CAGR > 20%) during 2004-2007, to consolidate and stabilize after 2008, as we can see on the Table below:

    Interface IP: PCI Express Wiki-pcie-table.jpg
    (1) Results extracted from the Gartner IP surveys in 2005, 2006, 2007 and 2008
    (2) Estimations and market share communicated to IPnest by the IP vendors

    We expect the 2010 results for PCIe IP to exhibit a 25% growth (IP market average growth in 2010) to reach just below $40M, and Synopsys to have consolidated the leader position.

    PCIe IP: PHY and Controller
    As most of the High Speed Serial Interface, the PCIe IP has been split into two parts: the PHY, a SerDes based and –mostly- mixed signal function, and the Controller, a fully digital function. Historically, these functions have been developed by distinct companies. In 2008, it was clear that the customers prefer to acquire an integrated function, to avoid any interoperability (between the PHY and Controller) issue, which explain the success of Synopsys, the reason why Rambus and ARM (providing the PHY only) decided to exit this market when Snowbush (a PHY IP only vendor) decided to acquire Asic Architect, a Controller only vendor, in July 2008. Only PLDA and Inventure (present in Japan only) are selling a Controller only solution, with a few other small IP vendors.

    Interface IP: PCI Express Wiki-pcie-ip-part.jpg

    IP vendor list

    They are clearly #1 on the overall PCIe IP market, one of their main advantage is to sell PHY + Controller + VIP = complete solution. On top of this technical competitive advantage, their strength is their very large, direct, sales channel, so they can access basically every company involved in ASIC design.
    Thus, except if they make a drastic change in their business strategy, they should keep or consolidate this leader position, and will tend to consolidate on the PCIe IP market the same dominant position they have on the Interface IP market in general.

    Snowbush was the first to support a Gen-3 solution, according with a PR dated June 8, 2009: “Snowbush jumps on PCI Express gen-3 early with PHY/controller IP”, the IP being used by PLX, a former customer of ARM. Snowbush has a strong PHY IP roadmap, completed with the Controller IP offer coming from the acquisition of Asic Architect in July 2008.

    ARM (Artisan)
    Being part of the top 3 in the Gartner surveys for 2006 and 2007, ARM has exited this market.

    Being the leader in the early days, Rambus has exited this market, which is not aligned with their business model of a “technology provider”, and no more an “IP vendor”.

    MENTOR Graphics
    The company has finally decided on the Feb’ 28th 2008 to exit the IP business and close the IPD.

    PLDA sales force and technical support, being strongly focused on PCI technologies, can be very successful on the market. They are just behind Synopsys on the “visible market” for the controller IP.

    INVENTURE, was called previously Zuken, is very active on their domestic market (Japan). They are selling a complete solution (PHY + Controller IP), the PHY IP coming probably from foundry (ies) who prefer to concentrate on their core business and let an IP vendor sub-licensee their product.

    Northwest Logic
    Has demonstrated the compliance with the ARM PHY (Feb, the 12th 2007) for an ASIC IP solution, is providing the x1, x4, x8 solution to the FPGA market, in particular through Lattice SC products.

    PHY IP sold by Foundries

    Here, we are addressing the part of the market which is hidden, because the customer will make no RFQ to an IP vendor, as far as the foundry can supply the PHY, either developed internally, either bought to an IP vendor under license term allowing the resale of the IP. It is to be noticed that the foundries have understood for a long time that they need to include Hard IP at their catalogue, so they are used to propose High Speed PHY. The list includes:
    • TSMC (and Global Unichip)
    • UMC (and Faraday)
    • IBM
    • SMIC
    Verification IP vendors

    Due to the cost and complexity involved in creating an internal solution, when they decide to run verification on a protocol, majority of teams chose to use an externally supplied verification IP (VIP) for Interface Protocol standards like PCIe, SATA or USB 3.0. Using externally supplied VIP has the additional benefit of providing an independently created model against which to validate the design IP. IP design teams that use their own internal model risk missing design flaws that an independent solution would commonly identify.


    Avery is supporting PCIe VIP since the introduction of the standard.
    Cadence (Denali)

    Their verification tool, Incisive ABA VIP uses assertion-based verification (ABV) techniques to identify bugs during simulation and acceleration, is compliant with the Open Verification Methodology (OVM), and supports multiple languages including SystemVerilog, e, Verilog®, and VHDL.

    They also provide, on a per protocol basis, test bench VIP, assertion-based VIP, transaction-based acceleration VIP.

    Mentor Graphics
    Mentor VIP for PCIe is part of the Questa product line. No information available about the Revenue on this segment for Mentor


    nVS, nSys’s verification IP for PCIe is based on Bus Functional Model (BFM) for RP or EP, Monitors, Assertions-based Checker and Test Suites. They offer the option of Source code in SystemVerilog both for OVM and VMM to comply with Assertion Based Methodology. As many VIP vendor, nSys is also offering design services for verification, that they call “Independent Verification services”.


    PerfectVIP deliver a SystemVerilog-based OVM compliant VIP. Their Verification IP products for PCI Express include:

    Interface IP: PCI Express Wiki-diagram-pcie.jpg


    The VIP is part of Design Ware. This means that the product is used (by the design team integrating PCIe from Synopsys) but not necessarily valorized, as it is sold with a bunch of IP and VIP.

    Eric Esteve

    Interface IP: PCI Express Wiki-logo-slogan-ipnest.jpg

    Attached Thumbnails Attached Thumbnails Interface IP: PCI Express Wiki-board-market.jpg  

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    Nice article!!

    I really want to thank the author for running such a nice wiki series. As a beginner I really was looking for such introductory articles.
    just one point, can you please upload larger version of Fig. 2? When I download and zoom it, it looses focus.
    Also, can you please post some reference material links, so if someone wants to go in detail s/he can refer those?

    Thank you again!

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