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Thread: Interface IP: MIPI wiki

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    Blogger Eric Esteve's Avatar
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    Interface IP: MIPI wiki

    MIPI is an Interconnect protocol offering several key advantages: strong modularity allowing minimizing power but also reaching high bandwidth when necessary (6 Gbps, 12 Gbps…), a guaranteed interoperability between an Application Processor and peripheral IC coming from different sources: Camera Controllers (CMOS Image Sensor), Display Controller, RF Modem, Audio Codec and so on as we will see later.

    According with the MIPI Alliance, the year 2009 has been the time for MIPI specification to be developed, when 2010 was dedicated to Marketing and Communication effort to popularize MIPI technologies within the SC industry, finally the year 2011 is expected to see MIPI deployment in the mass market, at least in the Wireless (Handset) segment at the beginning.

    Why MIPI?

    MIPI follows the trends in the Electronic industry: the massive move from parallel to serial interconnect, as illustrated by PCI Express replacing PCI, SATA replacing PATA, HDMI or DisplayPort replacing LVDS based interconnect to Display material (computer screen or HDTV) etc… Using similar technologies in Mobile Devices is a natural move, but a specific attention has been taken to power consumption. MIPI has been specifically designed for portable electronic devices, battery powered, and the power consumption is a key feature, all along the food chain, up to the end user who will buy –or not- a device in respect with the battery lifetime (when he probably does not care about the name of the core processor, ARM, Intel or MIPS being kind of “esoteric” notions for him, at least for the moment).

    Even if MIPI as an IP market is still at the infant stage, we expect it to strongly grow in 2011, starting in the wireless handset application, and more precisely in the Smartphone segment, which is by the way the most growing segment, seeing a 70% growth rate between 2010 and 2009, to reach slightly above 300 Million units sold! At first, we are taking a look at the IC shipment, as this is the indicator that MIPI as a technology is mature enough to allow production level close to 1 Billion units (in 2010). The MIPI technology has to be stable enough to allow such high production level, at every design stage: design integration and lay-out, manufacturing and last but not least, test in production.

    IPnest has built a forecast for MIPI powered IC in production, for 2010-2015.

    Interface IP: MIPI wiki-mipi-ic-forecast.jpg
    Another factor, probably the most important for the adoption of an emerging technology, is the fact that “MIPI powered” IC pricing, benefiting from the huge production quantities generated by the MIPI adoption in the wireless handset segment, is going down, or at least at the same level than a similar IC not supporting MIPI.

    Then you can take full benefit from MIPI usage:
    • Standardized Interconnect protocol: an OEM can run seamless integration in the system of the different IC, providing they comply with the same MIPI Interfaces.
    • As well, an OEM can easily move from one IC supplier to another for the same function (for example a camera controller IC)
    • There are different specification for the Controller (CSI, DSI, LLI and so on), but only two for the PHY (D-PHY and M-PHY): in that sense, MIPI is the Thunderbolt equivalent for the Mobile Electronic Devices. A unique PHY technology can support different functional needs to interface with Camera, Display, Modem, Mass Storage, WLAN, Remote Coprocessor…!
    WHAT is MIPI?

    MIPI is a bi-directional high speed serial differential signaling protocol, power consumption optimized and dedicated to the Mobile Devices, to be used to Interface chips within the system, at the board level. It uses a Controller (digital) and a mixed signal PHY. There are numerous specifications (DSI, CSI, DigRF, LLI…), but all of these rely on one of the two PHY specifications: D-PHY and M-PHY.

    M-PHY supports different modes of operation:
    • LP at frequency range of 10K-600Mb/s
    • HS at frequency range of 1.25 to 6 Gb/s
    The protocol is scalable, so you can implement one or more lanes in each direction, and then you implement the number of PHY “instances” related to the number of lanes you need to support the data bandwidth you need for a specific application.

    The D-PHY is still a valid protocol, currently used in production, but the way the M-PHY has been defined allows supporting the same bandwidth than the D-PHY, for the low data rate, up to a much higher bandwidth (data rate at 6 Gbps per lane). Thus we strongly guess that the M-PHY will be the unique PHY used for future applications, which is positive for every actors, IP vendors, IC suppliers and OEM. This is why we will concentrate on the M-PHY description, letting to the reader the possibility to take a look at the MIPI Alliance web site for D-PHY related information. See:

    Interface IP: MIPI wiki-m-phy-modules.jpg

    PHY Working Group is focusing on the development of the M-PHY. MIPI M-PHY is a high-frequency low-power, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The M-PHY can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and communication between Baseband to RFIC. It supports the following standards: DigRF v4, CSI-3, DSI-2, Uniport-M (UniPro1.5) and JC-64.1 UFS. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates. Please refer to the evolution graph for more information about the status.

    Interface IP: MIPI wiki-m-phy-roadmap.jpg

    MIPI Controller: to better understand the usage of the different Controller specifications, the figure showing the different MIPI interfaces in a Mobile Platform is very useful.

    Interface IP: MIPI wiki-mipi-interface-mobile.jpg

    MIPI IP Market

    Interface IP: MIPI wiki-mipi-ip-forecast.jpg

    Take a look at “MIPI IP survey” from IPnest

    MIPI powered IC Forecast 2010-2015
    IP Market Analysis: IP vendor competitive analysis, market trends
    MIPI IP 2010-2015 Forecast by Market segment:
    - Wireless Handset
    - Portable systems in Consumer Electronics
    - PC Notebook & Netbook, Media Tablets

    Verification IP vendors


    Avery is supporting PCIe and USB 2.0 and SATA VIP for several years; they now support USB 3.0 VIP (Verilog and SystemVerilog OVM/VMM).

    List of VIP from Avery:
    · PCI Express 1.1, 2.1, and 3.0
    · USB 2.0/OTG, 3.0, xHCI, and UAS
    · SATA 1,2,3
    · AMBA AHB and AXI3/4

    Avery does not propose design IP, neither design services.

    Their verification tool, Incisive ABA VIP uses assertion-based verification (ABV) techniques. Incisive VIP is compliant with the Open Verification Methodology (OVM), and supports multiple languages including SystemVerilog, e, Verilog®, and VHDL.

    They also provide, on a per protocol basis, test bench VIP, assertion-based VIP, transaction-based acceleration VIP. Back in October 2008, they have made several acquisitions of VIP products from HDL Design House, Yogitech SpA, IntelliProp Inc.

    The existing portfolio of Cadence UVCs supports AMBA AHB and AXI, Ethernet, PCI Express, PCI, and USB industry-standard protocols.


















    Register & Memory




    Serial Rapid I/O



    Cadence has even more heavily invested into this market with Denali acquisition in 2010 (for $315M), they bought a strong IP and VIP port folio and competencies, and probably good market share. This includes the Memory models, PCIe and USB VIP and DDRn functional IP.

    ExpertIO, Inc

    The list of VIP supported by ExpertIO, Inc includes:
    · PCIe Gen-2, Gen-3, Gen-3
    · Ethernet (MAC, 10/100/1000, XAUI, KX, KX4, KR, 40/100Gb)
    · Fibre Channel, SATA, SAS
    The company is also delivering design services in verification.


    nVS, nSys’s verification IP, consists of Bus Functional Model (BFM), Monitors, Assertions-based Checker and Test Suites. They offer the option of Source code in SystemVerilog both for OVM and VMM to comply with Assertion Based Methodology.

    The list of BFM supported by nSys includes PCI family (PCIe Gen-3/Gen-2/Gen-1, SR-IOV, PCI-X and PCI), ARM AMBA (AXI, AHB, APB), Storage (SAS 3.0, SATA 3, ATAPI), Communications (Ethernet 100/40/10/1G, Interlaken, SPI 4.2), USB 3.0 and USB 2.0, MIPI HSI, and others (I2C, SMBus, SDIO, UART).

    The company is also delivering design services in verification.


    PerfectVIP deliver a SystemVerilog-based OVM compliant VIP. Their Verification IP products include:

    Interfaces VIP

    Interface IP: MIPI wiki-diagram-ssu.jpg

    ·USB 3.0
    ·USB 2.0
    ·PCIe Gen-3, Gen-2, Gen-1
    ·SPI 4.2

    Storage VIP

    Interface IP: MIPI wiki-diagram-sas.jpg

    ·Fibre Channel

    Buses VIP

    Interface IP: MIPI wiki-diagram-amba.gif


    PerfectVIP offers full-service support for SOC and ASIC designs, from customer’s specification to GDSII with full verification in ASIC, FPGA, board design and Software and Firmware development.
    Sibridge technologies

    The company offer BFM based VIP. The list of BFM supported by Sibridge includes PCIe Gen-3/Gen-2/Gen-1, ARM AMBA (3/4 AXI, AHB, APB), Ethernet 100/40/10/1G & 10M/100M, USB 3.0 and USB 2.0, and others (I2C, SPI, UART).
    SmartDV technologies

    The company offer BFM based VIP in the following segments:
    · ONFI, NFC, eMMC, SDIO 1.0/2.0/3.0, Fibre Channel
    · Interlaken, SPI, Ethernet (MAC, 10/100/1000, XAUI, KX, KX4, KR,40/100, KR4, CR10)
    · I2C, SMBus, I2S, Opencore Wishbone B3, OCP, AMBA 4 AXI
    · USB 3.0, USB 2.0, DDR3, DDR2, RapidIO

    The company offer VIP through DesignWare.
    · Interfaces: MIPI DSI, HIS; HDMI 1.3; PCIe, PCI-X and PCI; USB 1.1, 2.0 and OTG;
    · Bus: I2C; AMBA PHB, APB, AXI; OCP
    · Networking: 802.3; Ethernet 10/100M/1/10G
    · Storage: SATA 1, 2, 3

    To find more information about the different Controllers, just follow the different links:
    There is also Controllers defined for specific (RF or Battery) or support functions (Test or Power Management). These are:

    By Eric Esteve

    Interface IP: MIPI wiki-logo-slogan-ipnest.jpg

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    Some clarification would be helpful regarding the specific, newer standards this article discusses versus the full range of specifications the MIPI Alliance covers.

    First, it's confusing to say MIPI is "an interface protocol" - it's not. The MIPI Alliance controls the specifications for a number of different interface standards, which include both physical/electrical requirements and protocol definitions. Second, the variety and complexity of these different standards is pretty broad, and they're somewhat unrelated (e.g. some are for RF front-end to transceiver or processor communication with low speeds, single-ended CMOS levels and small pin count, and others are very high speed differential serial interfaces for other purposes). For example, some of the RF front end standards, e.g. DigRF v1.12 and the MIPI RFFE standard, don't fit the blanket description in the article (e.g. "MIPI is a bi-directional high speed serial differential signaling protocol...").


    Q: What does "MIPI" stand for?
    A: MIPI is not an acronym and has no specific meaning. MIPI Alliance is focused on developing interface specifications for mobile devices. Propoer usage of MIPI are as follows:
    MIPI Alliance -- The organization.
    MIPI Member – Any company who joins the MIPI Alliance.
    MIPI Specification -- A specification adopted by the MIPI Alliance.

    Here's a list of the main standards, from:


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