You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

Results 1 to 1 of 1

Thread: Interface IP: DDR

  1. #1
    Blogger Eric Esteve's Avatar
    Join Date
    Nov 2010
    Marseille, France
    Thumbs Up
    Received: 111
    Given: 107

    Interface IP: DDR

    The Double Data Rate DRAM standard (DDRn where n can be 2, 3 or 4) is now in use for more than 15 years. The memory controller interface is certainly the most widely used if we look at the long list of Interface: PCIe, HDMI, USB, SATA, MIPI, DisplayPort and more, as we can make the assumption that for every System-on-Chip (SoC), you need to access an external DRAM. By definition, a SoC is an ASIC or ASSP including a microprocessor core, as well as additional functions called “peripheral”, by opposition of the heart of the system, the processor. When you use a processor, you most often need to use an external DRAM to store and manipulate the data. Even if we rank the Memory Controller Interface in the list of Interfaces functions, it strongly differs, as it is still based on a parallel data bus, with a separate clock. Because both phases of the clock are used to access the data, you can double the data rate in respect with the clock nominal frequency.

    Interface IP: DDR-ddr-trend-rambus.jpg

    Until recently, every senior design engineer could develop a memory controller function, when the data switching frequency was less than one GHz. It is becoming a lot more difficult to develop a memory controller in house and, even if you can find smart enough designer to do the job, developing such a function will not bring any differentiation, but it will keep busy some high level resources who could be assigned to the part of the ASIC or ASSP design which is the heart of the fabless or IDM know how. These are the main reasons why buying –a memory controller- is smarter than making. This is why we think the memory controller IP market has a bright future: you need one for every SoC developed, it is becoming more and more difficult to develop and the trend in the semiconductor is to focus the design resource on the differentiating part of the SoC (also because it would be impossible to develop the large IC of dozen of million gates, respecting the time-to-market requirements, by using internal developments, as you would need a design team of thousand engineers!).

    Interface IP: DDR-ddr-roadmapsnps.jpg

    Who is serving this IP market?
    Historically, RAMBUS has been very present in the DDR market as the memory products are the heart of the company know-how. But RAMBUS position as a “technology provider”, not as an IP vendor. Except if you have a few hundred million dollars to spend like did Samsung to license Rambus’ technology, you will have to go on the regular market. The market has consolidated recently, and there is now a handful of vendors: Cadence, Synopsys, ARM, Northwest Logic and a couple of companies specialized in high speed SerDes: Mosys and Analog Bits.
    When Cadence has acquired Denali for $315M, less than one year ago, one of the nuggets was the DDRn controller IP product line built by Denali during the last 10 years. Denali’ DDR controller IP was well known within the industry, doing pretty well with sales in 2009 estimated to be slightly less than $10M (even if Denali was one of the very few companies who constantly report to Gartner DDR Controller IP business results below the reality!). Their product was nice, but still based on a Soft PHY, making life more complicated for the designer having to integrate it. Synopsys DDR Controller IP (coming from the acquisition of MOSAID in 2007) was already based on a hard PHY, as well as Virage’ product (coming from the acquisition of INGOT in 2005). That’s why Denali had to build a partnership with MOSYS (in fact Prism Circuit before to be acquired in 2009) to offer a solution based on a hard PHY (from MOSYS) and their DDR3 Controller. Before the acquisition of Denali by Cadence (and Virage by Synopsys, by the way) in May 2010, the DDR Controller IP market was growing fast, and very promising, as we can see on the two figures.

    Interface IP: DDR-ddr-market-2008-2009.jpg

    DDRn IP market Forecast.

    In fact, if the number of ASIC and ASSP design start is declining, the proportion of SoC is growing faster, so the net count of ASIC integrating a processor (or Controller, DSP) core is growing. When you integrate a processor, you need to access an external memory (the cost of embedded DRAM being prohibitive) so you need to integrate a DDRn Controller. Considering the ever increasing memory Interface frequency, and the related difficulty to build a DDRn Controller in-house, the make vs buy question leads more frequently to an external solution, or to buy an IP. This is why the forecast for the DDR Controller IP market, even the more conservative, shows a x3 multiplication during the next 3 years. When we compare the DDR IP market with the other Interface IP market, we expect it to be the faster growing market.
    DDRn IP Market Forecast and comparison with the other Interface IP

    Interface IP: DDR-interface-forecast.jpg

    Take a look at “Interface IP survey – 2010-2015 Forecast” from IPnest for more information...

    Future of DDRn

    Intuitively, we feel that it will not be possible to indefinitely increase the data bandwidth by playing with either the bus width (the PCB routing will become unmanageable), or the clock frequency (to manage the skew between the clock and the data, you will have to set routing rules at the board level impossible to meet: a 2 GHz nominal clock, or 4 Gbs DDR, would require a maximum skew of 1/4th of the period, or 62.5 ps, which translated in track size on the board represent 5 or 6 mm) or even with the data rate. In every case, trying to increase the data bandwidth and still using a parallel bus with separated clock is equivalent to impose to the board layout a set of rules which becomes impossible to meet. This is why we think the interface with a DRAM will have to follow the same trends than the other interfaces: move to high speed serial, differential signaling. Both techniques are possible: the clock could be embedded with the data (CDR), or could still be separated. Several companies are working on different innovative protocols to create a new market and generate an associated new source of revenue. We can mention:
    • Rambus, which is not a surprise in the IP business in the field of DRAM, who is proposing (February the 8th, 2010) “Mobile XDR”, still using parallel bussing, but differential signaling and offering four time more bandwidth than LPDDR3.
    • Silicon Image, as well a technology leader for innovative IP, who has created “SPMT LLC” to propose Serial Port Memory Technology (SPMT), based on High Speed Serial Links running up to 7.5 Gbps and requiring a specific PHY (and Controller), said to use less pins, consume less power and offer a higher bandwidth than the traditional DDRn protocol.
    • MOSYS is now, after the acquisition of Prism Circuits, able to offer an innovative Chip to Chip SerDes protocol optimized for high-bandwidth, high-efficiency, and high-reliability memory transactions, using a CEI-6G-SR/CEI-11G-SR style electrical interface. This is NOT a new DRAM interface protocol, as it uses the well known 1T-SRAM IP technology to optimize the communication. As such, it targets Networking applications, and we mention it as it shows that for some applications, the move has already occurred, except that traditional DRAM cannot be used… as the product does not support differential serial signaling.

    What could be the time frame for such a move? The serial technology is ready, demonstrated and in production for years. We could easily imagine a new protocol for memory interfaces running at a frequency in the 5 to 8 GHz range, being modular (like PCI Express) so allowing data bandwidth up to 32 GBytes/s (for a 32 data link running at 8 Gbps). The problem is more a marketing issue with the DRAM manufacturers. Having worked for TI before they sell the DRAM business to Micron, I know that DRAM market is a day to day business, close to a stock exchange market, where the very long term is the quarter. Where nobody want to take any risk, as you can burn a fortune if you take the wrong decision… The fact Samsung has signed a multi years license with Rambus could be a positive sign for the change of protocol. Samsung is the undisputed #1 DRAM manufacturer, they have the power, and Rambus has certainly the technology needed to build a new protocol for DRAM interface. We just have to wait…

    Interface IP: DDR-logo44-slogan14-ipnest.jpg
    Eric Esteve IPnest
    Attached Thumbnails Attached Thumbnails Interface IP: DDR-logo-slogan-ipnest.jpg  

    0 Not allowed!

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts