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Thread: Interface IP: Compliance Wiki

  1. #1
    Blogger Eric Esteve's Avatar
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    Interface IP: Compliance Wiki

    Interface Protocol Compliance: Last but not least!

    The product marketing decision has been taken to integrate the latest version of the protocol standard –say USB 3.0, it could be PCIe gen-3, SATA 3 or any of the high speed wired Interfaces we have discussed so far in SemiWiki- the project manager is in the evaluation and acquisition process for the SuperSpeed Controller IP, the PHY IP or both, the design team is familiarizing with the new technology… everything is on track. Yes… except Compliance. If you did not plan a budget (and define the task in you project planner tool) for the SuperSpeed USB compliance campaign, you will have to do it, sooner or later. As you probably well know, the sooner you will integrate this task in your project, the lower are the probability that the project slip due to the lack of compliance…as when you have to add a missing task in emergency, the project schedule may be seriously impacted.

    If we come back to the different Interface standard, we can see that their lowest common denominator is the fact that the new standard releases call for higher data rate, every 18 months or so: SATA 3 is specified at 6 Gbps, PCIe gen-3 at 8 Gbps and so on.

    Test set up for measurement of Jitter and Eye opening for a PHY, as below, looks pretty complex...

    Interface IP: Compliance Wiki-jitter-test-set-up-small.jpg



    Higher data rate means new PHY design techniques (new PLL…), new architectures (Fast Forward Equalization (FFE)…), the new protocol release also impact the Controller design (a new release always lead to a more complex specification: PCIe gen-3 specification document is more than 1000 pages large…). For all these reasons, adopting a new interface standard, or the latest release of a standard already used in your product, brings a certain level of uncertainty, and consequently a certain level of risk. For you, for the validity of your product, and for your customers, who will integrate it in a larger system, and interface this system with other systems. The compliance concept has been adopted to remove this uncertainty and eliminate the risk for you and your customers. Who is responsible for the compliance process definition? The different organizations like PCI-SIG, MIPI Alliance, SATA-IO and more.

    Now, the main question is to know what make up compliance testing. This list, extracted from the PCI-SIG web site, gives a good idea of the different test to make to guarantee the compliance with the protocol specification:



    Electrical testing will verify the PHY compliance in term of signal integrity. Such test will be common to all kind of protocols, when the configuration testing is more specific to PCI Express. Because most of the new high speed Interface protocols are “layered based”, a concept coming from Telecommunication industry, the next two: “Link protocol testing” and “Transaction protocol testing” will also be found in the compliance program for other standard. The latest is specific to PCI Express. To summarize, a compliance program will verify the PHY (Electrical testing of signal integrity) and the Controller (Link Layer and Protocol layer testing in respect with the specification).

    To perform these compliance tests, a chip maker has two options: either to attend to a “Plug Fest”, organized in general twice a year by the standard organization, either to pass through one of the Test house, a qualified independent test lab responsible for the appropriate coordination with the standard organization regarding testing results and results submission.

    When the chip maker goes to a plug fest, where he will run the different interoperability test, he will follow this flow:




    Interface IP: Compliance Wiki-interopsubmission_sata-small.jpg


    If he decides to pass through an independent test lab, the overall process flow is described below:



    Interface IP: Compliance Wiki-interopsubmission_sata-tid-small.jpg


    The compliance process is one of the last step of the IC development, nevertheless it has to be taken into account early enough in the product development stage. This can be as early as during the Interface IP selection process, asking the question: does the IP vendor product has been certified? It can be also during the IP function integration in the SoC, as it may be necessary to implement an efficient test strategy to make the Interface function testable.



    Or it can be when the budget for the SoC is built, as the cost, both in resources and linked to the measurement apparels (Protocol analyzer and Signal Integrity analyzer) is strongly increasing with the protocol speed (PHY data rate). It may be the right time to think about passing through an independent test lab, and ask for a quotation…



    By: Eric Esteve from IPnest

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    Attached Thumbnails Attached Thumbnails Interface IP: Compliance Wiki-jitter-test-set-up.jpg  

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  2. #2
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    Compliance testing.

    Eric,

    One item not mentioned is Plugfest testing. This is where new IP is tried against existing products. I know this was invaluable for our team as well as our customers. Plugfests are part of the industry bodies that perform compliance testing and I do not believe they are planned everytime a compliance test is held. In addition, if an IP vendor misses the industry body testing (twice a year?), they can contract authorized test houses to perform the compliance testing (must more expensive route but available). If the authorized test house is used, you will not have plugfest testing.

    It's been a few years since I've been involved with this so you might want to get the above info validated.

    regard,
    Bill

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