EDA Company by Market Segment information, based on categories defined by EDAC.

Services


CAE Tools


Electronic System Level (ESL) Design, Synthesis and Verification

Software tools that design, model, simulate, create and/or analyze the functionality and performance of system-level designs (including elements of hardware and software), as well as the interaction of the hardware and software elements of these designs.


ESL Design

ESL Synthesis

ESL Verification and Prototyping


Design Entry Tools (Textual and Graphical)

HDL and Graphical Design Entry



IC Schematic Capture



Logic Verification


RTL Simulation



Dynamic Verification and Auxiliary RTL Simulation


Static Verification


Hardware-Assisted Verification


Other Logic Verification and Simulation Tools


Analog & Mixed Signal Simulators


Analog Simulators


Software tools that simulate only analog signals.

Mixed-Signal Simulators

Software tools that simulate mixed signals, i.e. both the analog and digital portions of a design. Includes interface packages for linking analog and digital signals.


RF Simulators

Software tools that simulate both at the circuit-level and/or system-level for RF/high-frequency and/or microwave designs. This category includes tools that perform linear frequency-domain simulation, harmonic-balance based simulators, circuit envelope simulators, RF/microwave transient/convolution simulators, and any RF/communication system-level simulators. It does not include tools defined in 2.6.5 as Analog and High-Frequency Analysis Tools.


EM Solvers, or Planar & 3D EM Solvers

Software tools that model and analyze the electrical characteristics and/or performance of physical geometries and/or structures, both 2-dimensional (2D, 2.5D) and/or 3-dimensional (3D), through electromagnetic techniques. This category excludes software tools identified as Parasitic Extraction Tools defined in 4.4.

Equivalency Checking

Software tools that use formal techniques to verify the functional equivalence of a design as it is transformed from one stage of the design process to the next. Includes RTL-to-RTL, RTL-to-Gate, Gate-to-Gate, etc.


Property Checking

Software tools that use formal analysis techniques -statically or in conjunction with other means such as simulation - to verify design properties such as assertions, assumptions, constraints, etc. used to define proper functional behavior of a design, which can be either user-specified or automatically extracted.


Analysis Tools

The tools in this category may work at any level of abstraction: behavioral, registertransfer-level (RTL), gate-level, or the physical layout of a device or system.


IC/ASIC Static Timing Analysis

Software tools that calculate delays (delay calculators) or detect timing violations in a digital design by checking the clock frequency with appropriate gate-level and interconnect delay models.


IC/ASIC Signal Integrity Analysis

Software tools used to analyze electrical signal behavior in wiring networks contained in integrated circuits (ICs); includes cross-talk and substrate noise analysis.


IC/ASIC Power Analysis and Optimization

Software tools that analyze, optimize, or diagnose power consumption and IR drop problems, or provide automatic power reduction in electronic circuits.


IC/ASIC Transistor-Level Simulation and Analysis

High-capacity circuit simulation tools designed specifically for timing and/or power analysis, that accept a SPICE netlist for input, and that handle capacities of a million or more transistors.

SPICE Circuit Simulation


Analog FastSPICE


FastSPICE

  • HSIM, Synopsys. Hierarchical.
  • NanoSIM, Synopsys.
  • XA, Synopsys. Next generation.
  • CustomSim, Synopsys. Combined: HSIM, NanoSim, XA.
  • UltraSim, Cadence. Hierarchical.
  • ADiT, Mentor.
  • FineSim PRO, Magma. Multi-CPU.
  • Turbo MSIM, Legend Design. Hierarchical.

Analog and High-Frequency IC/ASIC Analysis

An environment and its subtools dedicated to setting up and running analog, RF, and/or mixed-signal simulators and analyzing the results that are produced in either a manual or automated manner. Does not include simulation or analysis tools defined elsewhere.


Software products used to analyze electrical, thermal, EMC, power, and timing related to IC wiring networks. This category also includes tools used in conjunction with analysis, such as floorplanning, interconnect tracing, and topology extraction.


Design-for-Test and Test Automation Tools



ATPG

Automatic Test Pattern Generation for full-scan, partial-scan, and nonscan designs.


BIST



Memory

Insertion of circuitry or IP blocks that perform a Built-in Self-Test function for embedded and/or external memories.


Logic

Insertion of circuitry or IP blocks that perform a Built-in Self-Test function for random logic.


Mixed-Signal

Insertion of circuitry or IP blocks that perform a Built-in SelfTest function for mixed-signal circuits.

Scan

Internal

Insertion of internal scan circuitry to support ATPG or logic BIST.


Boundary

Insertion of IEEE 1149.1, 1149.6 or 1149.7 circuitry.


Fault Simulation and Other Test

Fault simulation/grading of functional vectors. Also includes methods or IP for test reuse, scan wrappers, pattern mapping, etc.


Synthesis

Logic Synthesis

Software tools that read a high-level electronic design description and implement it at a lower level of abstraction. Logic synthesis tools typically implement a design down to the gate level, and provide for logic optimization and library retargeting using a custom or ASIC design implementation.

FPGA Synthesis

Software tools that read a high-level electronic design description and implement it at a lower level of abstraction. FPGA synthesis tools typically implement a design down to the logic block level, and provide for logic optimization and block retargeting using a field programmable chip as the design implementation

Other CAE Hardware & Software

Any other CAE hardware or software tool not listed above.

PCB & MCM Layout Tools


PCB Schematic Entry

Printed Circuit Board (PCB) software products commonly known as schematic editors or schematic capture tools. This category also includes analog schematic entry, but not generic drawing packages.

PCB Analysis

Software products used to analyze electrical, thermal, EMC, power, and timing related to wiring networks in PCBs other PCB-related designs. This category also includes tools used in conjunction with analysis, such as PCB floorplanning, interconnect tracing, and topology extraction.

IC Package Analysis

Software products used to analyze electrical, thermal, EMC, power, and timing related to wiring networks in IC Packages, multi-chip packages or MCMs. This category also includes tools used in conjunction with analysis, such as floorplanning, interconnect tracing, and topology extraction.

Other System Interconnect Analysis


Software products used to analyze electrical, thermal, EMC, power, and timing related to wiring networks other than PCBs or IC Packages, including cables, harnesses, connectors, sockets, optics. This category also includes tools used in conjunction with
analysis, such as floorplanning, interconnect tracing, and topology extraction.

PCB Computer-Aided Manufacturing

Software tools used to interface design with manufacturing for PCB design.

PCB Physical Design

Physical design tools for the placement of physical components and/or the routing of interconnect signal traces on printed circuit board (PCB) assemblies. At a minimum, a PCB layout tool must have the capability to determine the placement of components or to route interconnect wiring. A PCB layout tool may include design rule checking, photoplotting output, provided that it handles layout.

IC Package Physical Design

Physical design tools for the placement of physical components and/or the routing of interconnect signal traces on IC Package or multi-chip package assemblies. At a minimum, a layout tool must have the capability to determine the placement of components or to route interconnect wiring. A layout tool may include design rule checking, mask outputs, and interfaces to manufacturing, provided that it handles layout.

Other Physical Design

Physical design tools for fabrics other than PCB and Packaging such as cables, harnesses, connectors, sockets, optics. This may involve placement of physical components and/or the routing of interconnect. May also include standalone design rule checking, mask outputs, and interfaces to manufacturing.

Library & Design Data Management

Descriptions and management of design elements used for designing physical interconnect systems. This category includes component models for simulation or analysis, symbols, component information systems, library development tools, library
management tools, and design libraries. It does not include semiconductor IP (SIP), blocks, or libraries used in IC design.

Other PCB & MCM Hardware & Software

Any other PCB & MCM hardware or software tool not listed above.

IC Physical Design & Verification Tools


Physical Implementation

Software tools that automatically perform the placement and routing of circuits on an integrated circuit (IC) or application-specific integrated circuit (ASIC). Includes tools for designing gate arrays, embedded arrays, standard cells, and irregularly-sized macro- or mega-cell blocks. Also includes software tools that analyze timing, size, power dissipation, and routability before detailed physical layout. These include tools that provide estimations of interconnect resistance, capacitance, and/or inductance. May also include tools that perform synthesis and placement (but not routing), solely for the purpose of creating high-level graphical depictions of the topology of an integrated circuit layout.

IC Full Custom Layout

Software tools for hand-crafted full-custom ICs. Includes polygon editors, symbolic editors, and compactors.

IC Layout Verification

Software tools that verify that the layout topology of circuits which has undergone placement, routing, and compaction does not violate any fabrication process rules, i.e. design rule checkers (DRC). Includes electrical rule checkers (ERC), which verify that no electrical rule violations have occurred, and layout-versus-schematic (LVS) checkers, which verify that the physical implementation of the design matches its logical implementation.

Parasitic Extraction

Software tools that translate IC layout data into networks of electrical circuit elements (transistors, resistors, and capacitors) and parasitic elements (interconnect capacitance, resistance, and inductance). These tools are used to model the timing, power, and signal behavior of the IC design. Includes network reduction tools and two-dimensional and three-dimensional field solvers.

RET EDA (Including OPC and PSM)

EDA software used for modifying full-chip production designs on an existing defined production process to enhance resolution, process-window, and ultimately yield. Reticle Enhancement Technology (RET) software supports the full-layer layout geometry manipulation and empirically-modeled simulation necessary for a range of RET layout modifications such as Optical Proximity Correction (OPC), Strong Phase Shift Mask (PSM), Attenuated PSM, Scattering Bars, and support for illumination patterns such as Quadrupole and Annular. Rule-based OPC tools are reported in the IC Layout Verification Tools (4.3) category. Model-based OPC tools are reported in this category.

Technology CAD (TCAD)

Software used for simulating, exploring, analyzing and optimizing device, process, and/or optical parameters during the process of researching and developing a new semiconductor process. These tools are never used for production processing of complete
IC designs, and are typically used only on very small test structures due to computational constraints and the complexity of simulation setup and calibration. The input parameters to simulation are numerous first-principle-type physical parameters rather than empirical, summary-type parameters. These tools are sometimes used for calibrating full-chip production software tools.

Mask Data Prep

Software used for modifying full-chip production designs from the physical designer's DRC-clean layout into the various modified layers required for IC manufacturing (geometry processing), and the software that is used in most, but not all, cases to translate the design data from the EDA-standard formats into proprietary mask-writer (fracturing) and mask-inspection formats, including proprietary machine formats. This category also includes software used for frame generation, reticle layout and floorplanning (reticle organization), wafer floorplanning, and optimization.

Yield Enhancement

Software tools that modify a physical layout to avoid manufacturing process vulnerabilities and improve chip yield. Excludes RET & OPC tools reported in 4.5.

Other IC/ASIC and FPGA Physical Design and Verification Tools

Any tools for IC/ASIC and FPGA physical design and verification and yield optimization that are not listed above.