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Thread: Design Automation Conference ( DAC ) Wiki

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    Design Automation Conference ( DAC ) Wiki

    The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. No less than 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with over 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design.

    Design Automation Conference ( DAC ) Wiki-51dac-logo.png

    Location: San Francisco, CA
    Twitter Hashtag: #51DAC
    • Full conference passes - 2,393
    • Exhibits-only passes - 1,650
    • Exhibitors booth staff - 2,658

    CompanyTopicAuthorDAC Trip Report(s)
    Industry#51DAC, #52DACDaniel NenniIn Case You Missed #51DAC
    AtrentaRTL SignoffDaniel PayneRTL Signoff Update from #51DAC
    Carbon DesignVirtual PrototypesDaniel PayneVirtual Prototype Update from #51DAC
    Fractal TechnologiesIP ValidationDaniel PayneStandard Cell, IO and Hard IP Validation update from #51DAC
    MethodicsIP managementDaniel PayneIP Management Update at DAC
    CadenceSPICEDaniel PayneWhat's New with Circuit Simulation for Cadence at DAC
    DARPA, PNNLWorkshopAntonino TumeoDAC Workshop on Suite of Embedded Applications and Kernels
    ANSYS/Apache DANoise-coupled AnalysisDaniel PayneNoise-Coupled Analysis for Automotive ICs at DAC
    Tanner EDAEDADaniel PayneAffordable AMS EDA Tools at DAC
    SynopsysPanelDaniel PayneAMS Panel at DAC: Micronas, Infineon, AMD, STMicroelectronics
    MunEDAHigh SigmaDaniel PayneHigh Sigma Yield Analysis and Optimization at DAC
    Mentor GraphicsIC DesignDaniel PayneDAC Update on IC Design Tools at Mentor
    Mentor GraphicsSPICEDaniel PayneAnalog FastSPICE Update at DAC
    Synopsys, GLOBALFOUNDRIESIoTDaniel PayneIoT Breakfast Panel at DAC
    Mentor GraphicsDRC, LVSDaniel PayneAn Update on Calibre at DAC
    CoventorMEMSDaniel PayneMEMS Update from DAC
    MagwelEDADaniel PayneEDA for Power Management ICs at DAC
    eSiliconServicesPaul McLellanGDS II Online for TSMC
    MultipleIoTPaul McLellanHogan's Internet of Things Panel
    MultipleAutoHolly StumpSeen at DAC! Self-Driving Cars –Victory Lap or Pile-Up?
    MultipleEditorialDaniel NenniThe Best and Worst of #51DAC!
    MultipleSystemCJohn SwanSystemC: User Group update from DAC
    MultipleEditorialPaul McLellanImpressions of #51DAC
    TravelEditorialPaul McLellanAdvice for Out-of-towners
    Gary SmithIndustryDaniel PayneGary Smith at DAC
    MultipleBookDaniel NenniFabless Book Giveaway at the #51DAC Network Reception!


    Design Automation Conference ( DAC ) Wiki-dac-2013.png

    Location: Austin, Texas

    • Full conference passes - 1,589
    • Exhibits-only passes - 2,364
    • Exhibitors booth staff - 1,998

    CompanyEDA or IPDAC Trip Report
    AldecFunctional VerificationMissed #50DAC? See Aldec Verification Sessions Online
    Hardware ProtoypingHW Prototyping and HLS at DAC
    Arcadia InnovationSTA ToolA New STA Tool at DAC, No Not Cadence
    ARMIPARM: AMBA 5, Cortex-A12, Mali, video, POP...
    IPARM Update at DAC
    AtrentaRTL Sign-OffDAC IP Workshop: Are You Ready For Quality Control?
    AusdiaSDC ConstraintsSoC Constraints, Design & Verification at DAC
    Berkeley DAAnalog FastSPICEAnalog FastSPICE at DAC
    CadenceStatic Timing AnalysisDAC: Tempus Lunch
    Circuit SimulationCircuit Simulation update from Cadence at DAC
    Custom IC DesignCustom Physical IC Design update from Cadence at DAC
    Concept EngineeringVisual DebugVisual AMS Debug, an update at DAC
    Dassault SystemesDesign ManagementAn EDA update from Dassault Systemes at DAC
    DXCorrPhysical IPPhysical IP Update at DAC
    EDACAssociationKaufman Award: Chenming Hu
    Fractal TechnologiesIP VerificationVerifying Standard Cell Libraries at DAC
    G-AnalogSPICE simulatorGPU-Based SPICE Simulator for IC Library Characterization
    Gary Smith EDAIndustry AnalystDAC: Gary Smith: Don't Give Away Your Models
    GLOBALFOUNDRIES14nm FinFETDeploying 14nm FinFETs in your Next Mobile SoC
    ICscapeEDA toolsEDA Tools from China at DAC
    InfiniscaleVariability AnalysisIC Variability Analysis at DAC
    InvarianEDA toolsAnalysis of Power, Thermal, EM, IR at DAC
    IP ExtremeIPDAC IP Workshop: Are You Ready For Quality Control?
    Mentor GraphicsIndustry VisionDAC: Wally's Vision
    DRC, LVSCalibre Update at DAC
    Circuit Simulation,
    Custom IC design
    Eldo and Pyxis from Mentor, DAC Update
    MethdodicsDMDesign, Test and Regression Management of SoCs at DAC
    - multiple -Embedded SWSo, where are all the EMBEDDED guys?
    OasysDesign ClosureSpeeding Design Closure at DAC
    Panel SessionFunctional VerificationHardware Assisted Verification
    ProPlusCircuit SimulationSPICE update from ProPlus at DAC
    Real IntentSoC Sign-OffSoC Sign-off, Real Intent at DAC
    Silicon FrontlineExtraction, ESD, ThermalA 3D Field Solver at DAC for Parasitic Extraction, Thermal and ESD Analysis
    SonicsIPDAC IP Workshop: Are You Ready For Quality Control?
    SynopsysCircuit SimulationAMS IC Simulation update From Synopsys at DAC
    14nm FinFETDeploying 14nm FinFETs in your Next Mobile SoC
    Custom IC DesignFujitsu, Mediatek, Richtek and Synopsys talk about Custom IC Design at DAC
    TektronixDebug ASIC PrototypesFull Visibility in ASIC Prototypes at DAC
    Tela InnovationsPower ReductionTela Innovations, DAC Update
    TSMCFoundryDAC IP Workshop: Are You Ready For Quality Control?


    Design Automation Conference ( DAC ) Wiki-dac-49.png
    Total conference attendance at the 2012 Design Automation Conference (DAC), the premier event on automation and design of electronic systems, increased by 16% compared to DAC 2011, according to the 49th DAC Executive Committee (EC). The 49th DAC exhibitor floor was open from June 4-6, 2012 at the Moscone Center in San Francisco, California, with technical sessions running from June 3-7.

    Preliminary attendance figures for the 49th DAC break down as follows:
    • Conference attendees – 1901, up 9%
    • Exhibits only passes – 2783, up 39%
    • Exhibitors booth staff – 2704, up 11%

    Networking opportunities abounded on the exhibit floor, in poster sessions, at the evening receptions, and in the technical sessions, proving that DAC is the conference to attend for electronic design and embedded systems and software.

    CompanyEDA or IPDAC Trip Report
    Ansys2.5D, 3D PowerTSMC Theater Presentation: Apache
    ARMSemiconductor IPMike Muller's ARM Keynote at DAC 2012
    AsygnAnalog MacromodelsAnalog Macromodels at DAC
    AtrentaSoft IP ValidationTSMC Theatre Presentation: Atrenta SpyGlass!
    SpyGlass by Atrenta
    Berkeley DAAnalog FastSPICETSMC Theater Presentation: Berkeley DA
    Analog FastSPICE update at DAC
    Cadence DesignIC module generatorsST Using Cadence IC Tools with Module Generators at DAC
    3D PackagingCadence/TSMC 3D
    Panel DiscussionCollaboration at 28nm, 20nm and 14nm: IBM, Cadence, ARM, GLOBALFOUNDRIES, Samsung
    Photo EssayPhoto Essay and Comments on DAC 2012 in San Francisco, CA
    CiranovaIC custom layoutTSMC Theatre Presentation: Ciranova!
    Custom IC Layout Automation at DAC
    Concept EngineeringSchematic visualizationFrom SPICE Netlist back to Schematics at DAC
    DACMarie Pistilli AwardBelle Wei Receives Marie Pistilli Award and is Interviewed
    Photo, VideoPhoto and Video overview of DAC 2012
    Dassault SystemsDesign Data ManagementDesignSync update from Dassault Systems at DAC
    DXCorrIP: LibrariesPhysical IP Not from ARM or Synopsys
    PartitioningPartitioning Panel
    Global UnichipIC Design ServicesTSMC Theater Presentation: Production Proven Design Services Driving SoC Innovation!
    IC ScapeIC schematic, layout, closure toolsSchematic, IC Layout, Clock and Timing Closure from IC Scape at DAC
    InfiniscaleMonte CarloFast Monte Carlo from Infiniscale at DAC
    Invarian3D Thermal and Stress3D Thermal and Mechanical Stress for IC Packaging at DAC
    IPL AllianceInteroperable PDKsIPL Alliance at DAC
    iROCSER simulationSoft Error Rate predicion Software
    JedatIC layoutIC Layout Tools from Japan at DAC
    Lorentz SolutionEM Design and AnalysisTSMC Theater Presentation: Lorentz Solution!
    Mentor GraphicsIC P&R, custom layout, SPICEA DAC Update on IC Layout and Circuit Simulation Tools
    Multi-PatterningDouble Patterning Technology at DAC
    Video: CEO InterviewWalden Rhines at DAC 2012
    AMS SimulationAMS Simulation Update from Mentor Graphics at DAC
    MethodicsDesign Data ManagementMethodics update at DAC
    MicroMagicIC layout1,000,000,000,000 Transistor IC Layout Editing at DAC
    MunEDATransistor OptimizationRobustness, Reliability and Yield at DAC
    NimbicEM SimulationElectromagnetic Simulation Update from Nimbic at DAC
    OasysLogic SynthesisChip Synthesis at DAC
    Oski TechnologyConsulting: FormalFinding RTL Bugs Live at DAC Using Formal Techniques
    ProPplusAnalog Fast SPICEFast Monte Carlo and Analog Fast SPICE from ProPlus at DAC
    PulsicP&RShape-based IC Routing at DAC
    SolidoDesign centeringEDA Tools to Optimize Memory Design, Size Standard Cells, Verify Low-Power Design, Center Analog Designs
    SpringSoftIC LayoutLaker IC Layout Update at DAC
    SymicaFast SPICEFast SPICE from Kiev at DAC
    SynopsysSPICEWhat's New With HSPICE at DAC?
    Panel DiscussionSamsung, Synopsys, GLOBALFOUNDRIES and ARM at DAC
    Z-CircuitCell characterizationIC Cell Library Characterization at DAC
    Attached Thumbnails Attached Thumbnails Design Automation Conference ( DAC ) Wiki-dac_50th_anniversary_logo_web.jpg   Design Automation Conference ( DAC ) Wiki-dac2014.png  

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