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  • Semiconductor IP

    by Published on 07-10-2018 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Semiconductor Services,
    4. Security,
    5. Intrinsix
    Article: Cadence, Synopsys, and Mentor on FinFETs-mirai-impact-min.jpeg

    You’re excited about the business potential for your cool new baby monitor, geo-fenced kid’s watch, home security system or whatever breakthrough app you want to build. You want to focus on the capabilities of the system, connecting it to the cloud and your ...
    by Published on 07-06-2018 10:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. SiFive,
    4. RISC-V
    Article: Wafer Costs: Out of Control or Not?-sifive-e2-series.jpg

    Fully configurable with advanced feature sets allows for broad applications, including microcontrollers, IoT, wearables, and smart cards

    The E20 and E21 add to the growing list of SiFive RISC-V cores addressing the embedded controller, IoT, wearables, smart toys. On June 25, DAC opening day, SiFive announced the availability of its E2 Core IP Series, configurable ...
    by Published on 07-05-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Cadence,
    5. Events
    Article: Cadence, Synopsys, and Mentor on FinFETs-caption1.jpg

    A chain is as strong as its weakest link. This phrase resonates well in Static Timing Analysis (STA) domain, though it is about accuracy rather than durability. As timing signoff step provides the final performance readings of a design, an STA outcome is as good as its underlying components. Aside from the parasitic extraction accuracy and a delay equation that should be consistent with the upstream place and route tool, design’s cell timing-model accuracy derived from the characterization runs is critical --and could be the weakest link if not handled properly.

    Characterization changing landscape and Cadence solution
    Library characterization is both time consuming and extremely compute-resource intensive task. Traditionally it involves non-trivial data preparations as designers need to deal with multiple process corners, simulation models or library versions, permutation of constraints and different data types. The introduction of advanced process nodes has been accompanied by more complex requirements related to the ultra low-voltage devices, complex library cells and process variability that further complicate the characterization effort. Moreover, designers still needs to ascertain that the generated simulation delays must be accurate and tightly aligned with the STA tool of choice.

    At DAC 2018, Cadence announced Liberate™ Trio Characterization Suite, the industry’s first unified library characterization tool that runs both statistical and nominal characterization in parallel and provides complete validation of standard cell libraries. The word trio in “Liberate Trio” implies the three critical characterization components the integrated tool has been designated to provide: complex characterization needs, variation modeling and validation.

    Integrated solution shorten characterization time

    The tool unified environment ensures data consistency across many PVTs and improves the overall turnaround time such as through the reuse of vectors from one corner for another corners. “The creation of accurate timing, power and noise models for advanced-node libraries is becoming increasingly complex,” said Vinod Kariat, corporate vice president of research and development at Cadence. “The Liberate Trio Characterization Suite simplifies library characterization by enabling characterization across multiple corners and natively integrating nominal and variation in the same run. This significantly improves turnaround time and ease of use.”

    Commenting on this release, Ron Moore, vice president of business planning, Physical Design Group, Arm said “Characterization is an extremely time-consuming activity with increasing corners, larger libraries, and new data formats. By using Arm’s Artisan Physical IP, we validated Cadence’s Liberate Trio Characterization Suite and saw a notable improvement in turnaround time using the same number of CPUs. This is an important step in continuing to deliver high-performance libraries to our mutual customers.”

    ML augmentation and cloud enablement
    In this release, Cadence also took Liberate into the mainstream AI driven solution space. Employing advanced machine learning techniques, Liberate uses smart interpolation to help determine and reduce the critical corners that need to be characterized.

    Seena Shankar, Cadence Sr. Principal Product Manager said, “With machine learning what we use is the data clustering technique to identify and predict the points for which the characterization should be done and anything in-between is interpolated well in the STA environment.”

    As part of Cadence Cloud portfolio, Liberate Trio has been fully optimized for running on cloud-based servers. Its distributed and massively parallel capabilities offers up to 3X performance increase by running corners in parallel and natively running concurrent statistical and nominal characterization. Characterization of a library containing over 1000 cells that would normally take weeks now can be turned around in days. Liberate on the Cloud has been tested, validated, and optimized to run with the leading infrastructure as a service providers.


    Differentiating features

    Aside from ML and cloud support, Liberate Trio provides several features that make it to standout from other characterization solutions:






























    ...
    by Published on 07-03-2018 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. CEVA,
    4. IoT Internet of Things
    Article: Cadence, Synopsys, and Mentor on FinFETs-24_06_18_dragonfly_nb2_target_markets_v1-min.jpg

    I wrote last month about CEVA’s Dragonfly-NB1 platform, a single-chip IoT solution supporting narrow-band cellular communication; this can meet aggressive total solution price-targets for high-volume deployment, long-range access and the low-power needed for 10+ year battery lifetimes. ...
    by Published on 06-26-2018 10:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Events,
    4. SiFive,
    5. RISC-V
    CES 2013 Trip Reports (Win an iPad Mini!)-dover_coreguard.jpg

    The second Bay Area RISC-V Meetup event was held at the DoubleTree Hilton in Burlingame on June 19 with about 150 attendees. This event was hosted by SiFive and started with a networking session. The topics and speakers for the evening were:

    • Commercial Software Tools - Larry Lapides, Imperas
    • Securing RISC-V Processors - Dan Ganousis, Dover Microsystems
    ...
    by Published on 06-26-2018 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Semiconductor Services,
    4. eSilicon,
    5. FinFET
    Article: Mentor @ the TSMC Open Innovation Platform Forum-example-hyperscale-data-center-asic.jpg

    We all know IP is critical for advanced ASIC design. Well-designed and carefully tested IP blocks and subsystems are the lifeblood of any advanced chip project. Those IP suppliers who can measure up to the need, especially at advanced process nodes, will do well, absolutely. ...
    by Published on 06-25-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. NetSpeed Systems,
    5. Artificial Intelligence
    Article: A Brief History of Apache Design-introducing-orion.ai-min.jpg

    When I first started working in the semiconductor industry back in 1982, I realized that there was a race going on between the complexity of the system being designed and the capabilities of the technology in the tools and systems used to design them. The technology ...
    by Published on 06-21-2018 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Mentor Graphics
    Article: Battling SoCs: QCOM vs NVDA vs Samsung-caption.jpg

    Functional and physical verification are easily the two long poles in most IC product developments. During a design implementation cycle, design teams tend to push physical verification (PV) step towards the end as it is a time consuming process and requires significant manual interventions.

    PV Challenges
    In the traditional physical design flow, ...
    by Published on 06-19-2018 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. ArterisIP,
    4. Automotive
    Article: Is the RTL Design Flow Broken?-ip-library-fmea-min.jpg

    In the course of building my understanding of functional safety, particularly with respect to ISO 26262, I have developed a better understanding of the design methods used to mitigate safety problems and the various tools and techniques ...
    by Published on 06-18-2018 10:00 AM
    1. Categories:
    2. Semiconductor IP
    Article: Is the RTL Design Flow Broken?-qualcomm-litigation-prediction-1-1.jpg

    The recent (since 2016) news about Apple, China, FTC and other organizations positioning in respect with IP are concerning, as it seems indicating that Intellectual Property in general (Design IP and Technology IP) is at risk. Let’s consider several facts through different cases, involving ARM, Qualcomm, Imagination ...
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