You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Events

    by Published on 07-16-2018 10:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. Semiconductor Advisors
    Article: Cadence, Synopsys, and Mentor on FinFETs-0_vlsi_2018_cfet_julien-ryckaert_page_02.jpg

    The 2018 VLSI Technology conference was held in Hawaii in June and is one of the premier conferences covering integrated circuit process technology and circuit design. The Complementary FET (CFET) is an emerging option to continue logic scaling into the next decade. At the conference imec, GLOBALFOUNDRIES, Tokyo Electron and Coventor presented “The Complementary FET (CFET) for ...
    by Published on 07-16-2018 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. Semiconductor Advisors
    -semicon-west.jpg

    The stock market hates uncertainty most of all. In the absence of the known, the market will assume the worst or close to it. Right now there is a lot of uncertainty that continues to have more downside beta than upside beta. Everybody we spoke to at Semicon wakes up in the morning wondering what tweet was sent ...
    by Published on 07-15-2018 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. Semiconductor Advisors
    -semicon-2018.jpg

    We attended Semicon West Monday and Tuesday, the annual show for the semi equipment industry. Its very clear from discussions with all our sources in the industry that confirm that Samsung has put the brakes on spending on memory and that message was reinforced by declines in their expected profitability due to weaker memory pricing. We maintain that a near ...
    by Published on 07-11-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Events
    Article: Fixing Double-patterning Errors at 20nm-dac-2018-jan-25-cadence-2.jpg

    I attended on Monday, June 25, DAC’s Opening Day, a Cadence-sponsored Lunch panel. Ann Steffora Mutschler (Semiconductor Engineering) was the Moderator and the Panelists were Jim Hogan (Vista Ventures), David Lacey (HP Enterprise), Shigeo Oshima (Toshiba Memory Corp), Paul Cunningham (Cadence).
    ...
    by Published on 07-11-2018 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. EDA Careers
    Article: Cadence, Synopsys, and Mentor on FinFETs-mark-gilbert.jpg

    Welcome to my newly relocated column, I am so excited about my new relationship with Daniel Nenni, and the other esteemed bloggers on SemiWiki. For those who do not know me, I have been a featured columnist on another EDA portal for the past 12-plus years, and in EDA for 20-plus years. ...
    by Published on 07-10-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Events,
    4. Intento Design
    Want to learn 20 nm layout techniques!-id-xplore-min.jpg

    My IC design career started out with circuit design of DRAMS, so I got to quickly learn all about transistor-level design at the number one IDM in the world, Intel at the time. In the early days, circa 1978 we circuit designers actually had few EDA tools, mostly a SPICE circuit simulator followed by manual extraction, manual netlisting, manual layout, manual DRC, and of course, manual transistor sizing. In 2018 the scene has changed for the ...
    by Published on 07-09-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Graphics,
    4. Events
    Article: Cadence, Synopsys, and Mentor on FinFETs-caption1.jpg

    Getting your tape-out done on time is hard, but can it be made easier? That was the main topic of Mentor’s Calibre Panel held at DAC 2018, attended by a few key players in IC design ecosystem: Bob Stear, VP of Marketing at Samsung represented the foundry side; from the IP side, Prasad Subramaniam, VP of eSilicon for R&D and Technology; and the fabless side, Satish Dinavahi, ...
    by Published on 07-09-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies,
    4. Events
    Article: Oasys RealTime Explorer-ip-quality-not-your-problem.jpg

    This year I signed books in the Fractal booth (compliments of Fractal) and let me tell you it was quite an experience. IP quality is a very touchy subject and the source of many more tape-out delays than I had imagined. As it turns out, commercial IP is the biggest offender which ...
    by Published on 07-05-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Cadence,
    5. Events
    Article: Cadence, Synopsys, and Mentor on FinFETs-caption1.jpg

    A chain is as strong as its weakest link. This phrase resonates well in Static Timing Analysis (STA) domain, though it is about accuracy rather than durability. As timing signoff step provides the final performance readings of a design, an STA outcome is as good as its underlying components. Aside from the parasitic extraction accuracy and a delay equation that should be consistent with the upstream place and route tool, design’s cell timing-model accuracy derived from the characterization runs is critical --and could be the weakest link if not handled properly.

    Characterization changing landscape and Cadence solution
    Library characterization is both time consuming and extremely compute-resource intensive task. Traditionally it involves non-trivial data preparations as designers need to deal with multiple process corners, simulation models or library versions, permutation of constraints and different data types. The introduction of advanced process nodes has been accompanied by more complex requirements related to the ultra low-voltage devices, complex library cells and process variability that further complicate the characterization effort. Moreover, designers still needs to ascertain that the generated simulation delays must be accurate and tightly aligned with the STA tool of choice.

    At DAC 2018, Cadence announced Liberate™ Trio Characterization Suite, the industry’s first unified library characterization tool that runs both statistical and nominal characterization in parallel and provides complete validation of standard cell libraries. The word trio in “Liberate Trio” implies the three critical characterization components the integrated tool has been designated to provide: complex characterization needs, variation modeling and validation.

    Integrated solution shorten characterization time

    The tool unified environment ensures data consistency across many PVTs and improves the overall turnaround time such as through the reuse of vectors from one corner for another corners. “The creation of accurate timing, power and noise models for advanced-node libraries is becoming increasingly complex,” said Vinod Kariat, corporate vice president of research and development at Cadence. “The Liberate Trio Characterization Suite simplifies library characterization by enabling characterization across multiple corners and natively integrating nominal and variation in the same run. This significantly improves turnaround time and ease of use.”

    Commenting on this release, Ron Moore, vice president of business planning, Physical Design Group, Arm said “Characterization is an extremely time-consuming activity with increasing corners, larger libraries, and new data formats. By using Arm’s Artisan Physical IP, we validated Cadence’s Liberate Trio Characterization Suite and saw a notable improvement in turnaround time using the same number of CPUs. This is an important step in continuing to deliver high-performance libraries to our mutual customers.”

    ML augmentation and cloud enablement
    In this release, Cadence also took Liberate into the mainstream AI driven solution space. Employing advanced machine learning techniques, Liberate uses smart interpolation to help determine and reduce the critical corners that need to be characterized.

    Seena Shankar, Cadence Sr. Principal Product Manager said, “With machine learning what we use is the data clustering technique to identify and predict the points for which the characterization should be done and anything in-between is interpolated well in the STA environment.”

    As part of Cadence Cloud portfolio, Liberate Trio has been fully optimized for running on cloud-based servers. Its distributed and massively parallel capabilities offers up to 3X performance increase by running corners in parallel and natively running concurrent statistical and nominal characterization. Characterization of a library containing over 1000 cells that would normally take weeks now can be turned around in days. Liberate on the Cloud has been tested, validated, and optimized to run with the leading infrastructure as a service providers.


    Differentiating features

    Aside from ML and cloud support, Liberate Trio provides several features that make it to standout from other characterization solutions:






























    ...
    by Published on 07-04-2018 05:00 AM
    1. Categories:
    2. Events
    Article: Cadence, Synopsys, and Mentor on FinFETs-moscone-center-west.jpg

    Driving into DAC on Sunday afternoon was a chore since Gay Pride week was finishing with the Gay Pride Parade. Streets were closed, traffic was crazy, and people were roller skating naked which seems wrong on so many levels. This year the opening ceremonies were in the convention center hallway which ...
    Page 1 of 50 12311 ... LastLast