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  • Cadence

    by Published on 07-11-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Events
    Article: Fixing Double-patterning Errors at 20nm-dac-2018-jan-25-cadence-2.jpg

    I attended on Monday, June 25, DAC’s Opening Day, a Cadence-sponsored Lunch panel. Ann Steffora Mutschler (Semiconductor Engineering) was the Moderator and the Panelists were Jim Hogan (Vista Ventures), David Lacey (HP Enterprise), Shigeo Oshima (Toshiba Memory Corp), Paul Cunningham (Cadence).
    ...
    by Published on 07-05-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Cadence,
    5. Events
    Article: Cadence, Synopsys, and Mentor on FinFETs-caption1.jpg

    A chain is as strong as its weakest link. This phrase resonates well in Static Timing Analysis (STA) domain, though it is about accuracy rather than durability. As timing signoff step provides the final performance readings of a design, an STA outcome is as good as its underlying components. Aside from the parasitic extraction accuracy and a delay equation that should be consistent with the upstream place and route tool, design’s cell timing-model accuracy derived from the characterization runs is critical --and could be the weakest link if not handled properly.

    Characterization changing landscape and Cadence solution
    Library characterization is both time consuming and extremely compute-resource intensive task. Traditionally it involves non-trivial data preparations as designers need to deal with multiple process corners, simulation models or library versions, permutation of constraints and different data types. The introduction of advanced process nodes has been accompanied by more complex requirements related to the ultra low-voltage devices, complex library cells and process variability that further complicate the characterization effort. Moreover, designers still needs to ascertain that the generated simulation delays must be accurate and tightly aligned with the STA tool of choice.

    At DAC 2018, Cadence announced Liberate™ Trio Characterization Suite, the industry’s first unified library characterization tool that runs both statistical and nominal characterization in parallel and provides complete validation of standard cell libraries. The word trio in “Liberate Trio” implies the three critical characterization components the integrated tool has been designated to provide: complex characterization needs, variation modeling and validation.

    Integrated solution shorten characterization time

    The tool unified environment ensures data consistency across many PVTs and improves the overall turnaround time such as through the reuse of vectors from one corner for another corners. “The creation of accurate timing, power and noise models for advanced-node libraries is becoming increasingly complex,” said Vinod Kariat, corporate vice president of research and development at Cadence. “The Liberate Trio Characterization Suite simplifies library characterization by enabling characterization across multiple corners and natively integrating nominal and variation in the same run. This significantly improves turnaround time and ease of use.”

    Commenting on this release, Ron Moore, vice president of business planning, Physical Design Group, Arm said “Characterization is an extremely time-consuming activity with increasing corners, larger libraries, and new data formats. By using Arm’s Artisan Physical IP, we validated Cadence’s Liberate Trio Characterization Suite and saw a notable improvement in turnaround time using the same number of CPUs. This is an important step in continuing to deliver high-performance libraries to our mutual customers.”

    ML augmentation and cloud enablement
    In this release, Cadence also took Liberate into the mainstream AI driven solution space. Employing advanced machine learning techniques, Liberate uses smart interpolation to help determine and reduce the critical corners that need to be characterized.

    Seena Shankar, Cadence Sr. Principal Product Manager said, “With machine learning what we use is the data clustering technique to identify and predict the points for which the characterization should be done and anything in-between is interpolated well in the STA environment.”

    As part of Cadence Cloud portfolio, Liberate Trio has been fully optimized for running on cloud-based servers. Its distributed and massively parallel capabilities offers up to 3X performance increase by running corners in parallel and natively running concurrent statistical and nominal characterization. Characterization of a library containing over 1000 cells that would normally take weeks now can be turned around in days. Liberate on the Cloud has been tested, validated, and optimized to run with the leading infrastructure as a service providers.


    Differentiating features

    Aside from ML and cloud support, Liberate Trio provides several features that make it to standout from other characterization solutions:






























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    by Published on 06-25-2018 07:45 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Events
    Most of the re-spins are due to Functional defects?-cacence-cloud-slide.jpg

    The first clue was cloud vendors (Amazon, Google, IBM, etc…) at 55DAC for the first time ever with lots of cloud content including a Design on Cloud Pavilion. The second clue was the pre-briefing from Cadence last week. There has also been a lot of cloud chatter in the semiconductor ecosystem ...
    by Published on 05-29-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    Article: Predictions are hard, especially about the future-cornflakes-min.jpeg

    Logic simulation is a victim of its own success. It has been around for at least 40 years, has evolved through multiple language standards and has seen significant advances in performance and major innovations in testbench standards. ...
    by Published on 05-28-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Mentor Graphics,
    5. Synopsys
    Most of the re-spins are due to Functional defects?-eda-cloud.jpg

    There is an interesting discussion in the SemiWiki forum about EDA and the foundry business model which got me to thinking about the next disruptive move for the semiconductor industry. First let’s look at some of the other disruptive EDA events that I experienced firsthand throughout my 30+ year career. ...
    by Published on 05-21-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Events,
    5. Automotive,
    6. Artificial Intelligence
    Article Preview

    The recent fatal accident involving an UBER autonomous car, was reportedly not caused - as initially assumed - by a failure of the many sensors on the ...
    by Published on 05-17-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Automotive
    Article: The First 14nm FinFET Wafer Sighting!-caption.jpg

    This week Cadence introduced Legato™ Reliability Solution, intended to address increased challenges in designing high-reliability analog and mixed-signal ICs for automotive, industrial, aerospace and defense applications.
    ...
    by Published on 05-01-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Events
    CES 2013 Trip Reports (Win an iPad Mini!)-caption.jpg

    At CDNLive Silicon Valley 2018, I talked with Yuval Shay, Director of Product Management of Cadence Custom IC & PCB Group to scope out some more details on the recent Virtuoso product refresh announced earlier in the morning by Cadence Sr. VP & GM of the same group, Tom Beckley.

    Tom shared his view on enabling the fourth industrial revolution (4IR). He illustrated the challenges faced by both the system ...
    by Published on 04-30-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. FinFET
    Article: TSMC Apple Rumors Debunked!-3nm-processor-test-chip.jpg

    One of the more frequent questions I get, “What is next after FinFETs?” is finally getting answered. Thankfully I am surrounded by experts in the process technology field including Scotten Jones of IC Knowledge. I am also surrounded by design enablement experts so I really am the man in the middle which brings us to a discussion between Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence, Peter Debacker R&D team leader at imec, and SemiWiki on the 3nm testchip announcement.
    ...
    by Published on 04-24-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Automotive
    Which way the semiconductor industry is going?-india-traffic-min.jpeg

    While at DVCon I talked to Apurva Kalia (VP R&D in the System and Verification group at Cadence). He introduced me to the ultimate benchmark test for self-driving – an autonomous 3-wheeler driving in Delhi traffic. If you’ve never visited India, the traffic there is quite an experience. ...
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