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  • Daniel Payne

    by Published on 06-14-2011 12:40 PM
    1. Categories:
    2. Semiconductor Design,
    3. Tanner EDA
    iPDK is the way to go for AMS Designs-ic-design-flow2.jpg

    For 22 years now Tanner EDA has been in the business pf offering tools for AMS and MEMS designers. I learned what's new at DAC on Tuesday morning.

    Nicholas Williams – Director of Product Management

    Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
    W-Edit – is the waveform viewer

    Who is Tanner – full suite for custom IC design
    - 22 years in industry
    - AMS focus
    - First on Windows (also Linux)
    - 20K licenses, 67 Countries

    S-Edit – Schematics (Import Mentor and Cadence legacy data)
    - Cross probe between schematics and layout
    - Checking ...
    by Published on 06-14-2011 11:03 AM
    Semicoductor Market Outlook in 2011 - 2012-technology1.jpg

    It's all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what's new for 2011.


    What’s New in 2011 at Blue Pearl Software

    New designer experience, ease of use. Brand new GUI.

    Work with RTL to synthesis tools to get best timing in your layout.

    GUI – windows 7 and Linux, same look and feel.
    - All new in 2011
    - Inline help

    Blue Pearl Analyze – Linting, race checks,
    - Demo: support languages: ...
    by Published on 06-14-2011 10:43 AM

    Dipesh Patel, VP Engineering, ARM Physical IP

    Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

    Processor speeds: 1GHz to 1.5GHz
    SOC Memory: 600MHz to 1.2 GHz
    How power efficient?
    How is the layout density?

    Standard Cells: multi-channel, multi-vt (4) libraries

    Memory Compilers: single port, multi port, ROM
    7 families to choose from

    28nm libraries nominal VDD of 1.0V

    Processor Optimization Package (POP)
    - Physical IP
    - Reference ...
    by Published on 06-14-2011 10:26 AM
    Article: TSMC Versus The FabClub!-dac-tuesday-28nm.jpg

    The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

    Why 32/28nm
    - Lower power, high integration requirements, mobile applications

    What is Ready?
    - IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
    - August 2010 SNPS and GLOBALFOUNDRIES at 28nm
    - June 2011 SNPS and ARM at 28nm (A15 core)
    - June 2010 Samsung at 32nm with SNPS tools
    - Common Platform – Lynx tool flow is ready, January 2011
    - June 2011 GLOBALFOUNDRIES ready at 28nm
    - Samsung qualifies 28nm
    - Samsung at 35 tape outs at 32nm to date

    Anna Hunter, VP Samsung
    Technology Roadmap
    - 32nm LP: ready, HKMG process
    o SRAM at .149um*um, tiny size
    o Good yield at 86%
    o Matches SPICE results
    - 28nm LP: ready
    o Same HKMG as 32nm node
    o Works with ARM IP and SNPS tool flow
    - 28nm LPH: under development (low power, plus higher performance modules)
    o Will be up to 50% faster (with more leakage, 2.3X)
    o Same HKMG
    o Added strain to silicon
    o Shuttles starting now
    - 20nm LPM: in development, PDK evaluation now. Ready by end of 2012.

    Lynx – flow of SNPS tools and IP management, used by Samsung internally too

    ARM CPU – 45nm >1GHz on Cortex A9
    - 32/28nm >1.35GHz on Cortez A15
    - 28nm LPH, >2.0GHz Cortex A15

    IP Portfolio – High Speed, Memory, Mixed Signal
    - ARM, SNPS<

    Going from 45nm to 32nm more than 50% improvement in SRAM bit cell size

    Turn key solutions from Samsung
    - Design, Fab, Wafer Sort, Assembly, Final Test
    - Working on TSV technology for higher integration on packaging

    MPW – Run every quarter for 32nm and 28nm
    - Will start 20nm in September

    Fab sites – Korea( 20nm), Texas (40K wafers per month)

    Jim Ballingall, VP Marketing at GLOBALFOUNDRIES
    - AMD lead product used HKMG technology, quad core CPU with GPU integrated, 500GFlops, for notebooks
    - Llano powered laptops later in June

    Super Low Power – 28nm SLP (doesn’t use stressing), about 2.3GHz

    High Performance Plus – 28nm HPP (uses stressing), about 3.1GHz

    Global Solutions – Design
    by Published on 06-13-2011 04:34 PM
    Semicoductor Market Outlook in 2011 - 2012-cyber-eda-monday.jpg

    I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.


    2010 – Announced a debugger

    2011 ADDS Debugger – trace at the transistor level your design
    - Signal tracing
    - Post-layout debug

    o Tracing – which signal triggered that net that rose or ...
    by Published on 06-13-2011 04:08 PM
    Semiconductor Waste ...-qcp-diagram.jpg

    John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.

    John Schritz – Sr AE
    Ralph Iverson, Ph. D. (wrote QuickCap)

    John Schritz
    - Digital Signoff, extraction
    - QCP: 2.5D RC for full ASIC designs
    - QuickCAP NX: 3D field solver
    - QCP:

    Demo – 1.5 million instance design, 1.59 million nets, fully P&R, three libraries
    - QCP: Gate Level (Star RC competitor)
    - QuickCapNX: 3D field solver (Raphael competitor)
    - QCP TX: Transistor Level (RC XT competitor)
    - QCP ...
    by Published on 06-13-2011 03:53 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    Android Tablets?-hspice-guys-monday.jpg

    Hany El Hak – Product Marketing Manager

    Frederik Iverson – AE

    Scott Wetch – HSPICE Architect

    HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.

    Synopsys AMS Portfolio – wide range of tools
    - Custom Designer: IC schematic and layout tools
    - HSPICE – circuit simulation
    - CustomSim – full chip circuit simulation
    - IC Validator/Star RC – extraction, DRC, LVS

    HSPICE – Golden SPICE standard for about 30 years now, the same tool the foundry used to create their ...
    by Published on 06-13-2011 03:45 PM
    1. Categories:
    2. Semiconductor IP,
    3. ARM
    EDA 360 Discussion-john-heinlein.jpeg

    After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division

    Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).

    Q: Do you favor any EDA tools for creating your IP?
    A: No, we don’t really endorse a specific EDA vendor tool or flow.

    Q: What's new at ARM for 2011?
    A: Just started Process Optimization ...
    by Published on 06-13-2011 03:09 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    Android Tablets?-dac-ipl-luncheon.jpg

    Lunch time Monday at DAC and I learned about what's new at the IPL Alliance in 2011.

    IPL Sponsors: Magma, Mentor Graphics, Springsoft, Accelicon, Ciranova, Synopsys, TSMC, TowerJazz, Jedat, Tanner EDA

    Two major projects:
    1) iPDKS
    2) Analog Constraints
    by Published on 06-13-2011 02:58 PM
    EDAC CEO Forecast Event Report!-dac-magma-finesim.jpg

    At DAC I spent time in the Magma FineSIM demo suite on Monday morning.

    Greg Curtis – Product Director, Custom Design Business Unit

    - Talus for Digital Design
    - FineSim does: SPICE, FastSPICE, Characterization
    - Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
    - What’s New in FineSim?
    o RF
    o TCL circuit checks
    - ADC design trends
    o Parasitics dominate performance now
    o Sensitivity to noise and cross talk
    o Operating at low power
    o Requires more SPICE,
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