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  • Daniel Payne

    by Published on 06-17-2011 02:42 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    SPICE, Fast SPICE and Analog Fast SPICE-dac-snps-wed-breakfast.jpg

    My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.

    Interconnect Modeling
    - Open Source Interconnect Technology Format (ITF)
    o Used by Star RC
    - Modeling parasitic of interconnect
    - Interconnect Modeling Technical Advisory Board founded, meet twice per year
    o Program of IEEE-ISTO
    o Andy Brotman, VP Design Infrastructure at GF
    IMTAB – foundry perspective
    Design starts are slowing in number for each new node (although each new node has more devices)
    Need to avoid risks, ensure 1st silicon success
    Mistakes are more costly (NRE)
    Parasitic variation increases
    by Published on 06-17-2011 02:20 PM
    iPDK is the way to go for AMS Designs-dac-micro-magic.jpg

    Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.

    Karen Mangum

    I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

    Max-3D – Can handle stacked wafers with TSV
    - Gary Smith’s list of must-see for 3D
    - New for 2011: 3D Floor planner
    o Mostly ...
    by Published on 06-17-2011 02:01 PM
    Tsmc versus fabclub-dac-bda-simon-young.jpg

    Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).


    Quarterly release: 2011 Q2 now

    Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools

    Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.

    Device Noise – three ways to compute noise: ...
    by Published on 06-14-2011 01:14 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    iPDK is the way to go for AMS Designs-icvalidator_ds-fig1.jpg

    At DAC last week I visited the Synopsys demo suite to see what's new with IC Validator.

    Stelios Diamantidis, PMM
    - In-design physical verification
    - Sign-off reveals thousands of late stage DRC violations
    - 28nm has 1.5K rules, 15K runset sizes
    - Metal Fill changes timing
    - The DRM can be changed throughout the life of the process

    Timing Closure – can be too slow, too many iterations, too time consuming
    - A new methodology is needed

    IC Validator – verify as you go, early, not at the end of routing
    - Run during: Floorplan, P/G, ...
    by Published on 06-14-2011 01:01 PM
    Tsmc versus fabclub-extreme-da-flow.jpg

    Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.


    GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.
    - Sold stand alone.
    - Fast run times. ...
    by Published on 06-14-2011 12:40 PM
    1. Categories:
    2. Semiconductor Design,
    3. Tanner EDA
    iPDK is the way to go for AMS Designs-ic-design-flow2.jpg

    For 22 years now Tanner EDA has been in the business pf offering tools for AMS and MEMS designers. I learned what's new at DAC on Tuesday morning.

    Nicholas Williams – Director of Product Management

    Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
    W-Edit – is the waveform viewer

    Who is Tanner – full suite for custom IC design
    - 22 years in industry
    - AMS focus
    - First on Windows (also Linux)
    - 20K licenses, 67 Countries

    S-Edit – Schematics (Import Mentor and Cadence legacy data)
    - Cross probe between schematics and layout
    - Checking ...
    by Published on 06-14-2011 11:03 AM
    Semicoductor Market Outlook in 2011 - 2012-technology1.jpg

    It's all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what's new for 2011.


    What’s New in 2011 at Blue Pearl Software

    New designer experience, ease of use. Brand new GUI.

    Work with RTL to synthesis tools to get best timing in your layout.

    GUI – windows 7 and Linux, same look and feel.
    - All new in 2011
    - Inline help

    Blue Pearl Analyze – Linting, race checks,
    - Demo: support languages: ...
    by Published on 06-14-2011 10:43 AM

    Dipesh Patel, VP Engineering, ARM Physical IP

    Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

    Processor speeds: 1GHz to 1.5GHz
    SOC Memory: 600MHz to 1.2 GHz
    How power efficient?
    How is the layout density?

    Standard Cells: multi-channel, multi-vt (4) libraries

    Memory Compilers: single port, multi port, ROM
    7 families to choose from

    28nm libraries nominal VDD of 1.0V

    Processor Optimization Package (POP)
    - Physical IP
    - Reference ...
    by Published on 06-14-2011 10:26 AM
    Article: TSMC Versus The FabClub!-dac-tuesday-28nm.jpg

    The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

    Why 32/28nm
    - Lower power, high integration requirements, mobile applications

    What is Ready?
    - IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
    - August 2010 SNPS and GLOBALFOUNDRIES at 28nm
    - June 2011 SNPS and ARM at 28nm (A15 core)
    - June 2010 Samsung at 32nm with SNPS tools
    - Common Platform – Lynx tool flow is ready, January 2011
    - June 2011 GLOBALFOUNDRIES ready at 28nm
    - Samsung qualifies 28nm
    - Samsung at 35 tape outs at 32nm to date

    Anna Hunter, VP Samsung
    Technology Roadmap
    - 32nm LP: ready, HKMG process
    o SRAM at .149um*um, tiny size
    o Good yield at 86%
    o Matches SPICE results
    - 28nm LP: ready
    o Same HKMG as 32nm node
    o Works with ARM IP and SNPS tool flow
    - 28nm LPH: under development (low power, plus higher performance modules)
    o Will be up to 50% faster (with more leakage, 2.3X)
    o Same HKMG
    o Added strain to silicon
    o Shuttles starting now
    - 20nm LPM: in development, PDK evaluation now. Ready by end of 2012.

    Lynx – flow of SNPS tools and IP management, used by Samsung internally too

    ARM CPU – 45nm >1GHz on Cortex A9
    - 32/28nm >1.35GHz on Cortez A15
    - 28nm LPH, >2.0GHz Cortex A15

    IP Portfolio – High Speed, Memory, Mixed Signal
    - ARM, SNPS<

    Going from 45nm to 32nm more than 50% improvement in SRAM bit cell size

    Turn key solutions from Samsung
    - Design, Fab, Wafer Sort, Assembly, Final Test
    - Working on TSV technology for higher integration on packaging

    MPW – Run every quarter for 32nm and 28nm
    - Will start 20nm in September

    Fab sites – Korea( 20nm), Texas (40K wafers per month)

    Jim Ballingall, VP Marketing at GLOBALFOUNDRIES
    - AMD lead product used HKMG technology, quad core CPU with GPU integrated, 500GFlops, for notebooks
    - Llano powered laptops later in June

    Super Low Power – 28nm SLP (doesn’t use stressing), about 2.3GHz

    High Performance Plus – 28nm HPP (uses stressing), about 3.1GHz

    Global Solutions – Design
    by Published on 06-13-2011 04:34 PM
    Semicoductor Market Outlook in 2011 - 2012-cyber-eda-monday.jpg

    I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.


    2010 – Announced a debugger

    2011 ADDS Debugger – trace at the transistor level your design
    - Signal tracing
    - Post-layout debug

    o Tracing – which signal triggered that net that rose or ...
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