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    by Published on 08-17-2018 10:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Semiconductor Services,
    4. eSilicon,
    5. FinFET
    Article: FD-SOI is Worth More Than Two Cores-esilicon-serdes-7nm.jpg

    The Linley Group is an industry-leading source for independent technology analysis of semiconductors for networking, communications, mobile, and data-center applications. Their Microprocessor Report is widely read as a source of un-biased, no-nonsense analysis of technologies ...
    by Published on 08-17-2018 05:00 AM
    1. Categories:
    2. Wally Rhines
    Article: Mobile SoCs: Two Cores are Better Than Four?-rich-templeton-ti.jpg

    This is the eleventh in the series of "20 Questions with Wally Rhines"

    In high technology, there are numerous instances of highly productive groups coming together and generating game-changing ideas and products. This happened at Shockley Semiconductor in the 1960s when Gordon ...
    by Published on 08-16-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys,
    4. Automotive
    Article: Mobile SoCs: Two Cores are Better Than Four?-adas-min-l1l.jpg

    From my restaurant seat today in Lake Oswego, Oregon I watched as an SUV driver backed out and nearly collided with a parked car, so I wanted to wave my arms or start shouting to the driver to warn them about the collision. Cases like this are a daily occurrence to those of us who drive or watch other drivers on the road, so the promises of using Advanced Driver Assistance Systems (ADAS) is especially relevant in keeping us alive and injury free. I did some online research to better understand ...
    by Published on 08-16-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor Services,
    4. ANSYS, Inc.,
    5. eSilicon
    Article: Common Platform Technology Forum February 5th 2013 Live or Online!-dc-power-integrity-min.jpg

    While I missed ANSYS (and indeed everyone else) at DAC this year, I was able to attend the ANSYS Innovation Conference last week at the Santa Clara Convention Center. My primary purpose for being there was to listen to a talk by eSilicon ...
    by Published on 08-15-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Magillem,
    4. ArterisIP
    Article: Mobile SoCs: Two Cores are Better Than Four?-caption1.jpg

    Deterministic, yet versatile. Robust and integrated, yet user-friendly and easily customizable. Those are some desirable characteristics of an EDA solution as the boundaries of our design optimization, verification and analysis keep shifting. A left shift driven by a time-to-market schedule compression, while the process and application complexities keep pushing it in the opposite direction. ...
    by Published on 08-15-2018 05:00 AM
    1. Categories:
    2. General
    Which way the semiconductor industry is going?-silicon-valley-innovation.jpg

    Silicon Valley well exemplifies the saying “The more things change, the more they stay the same”. Very little has changed over the past decade, with the Valley still mired in myth and stale stereotype. Ask any older entrepreneurs or women who have tried to get financing; they will tell you of the walls they keep hitting. Speak to VCs, and you will realize that they still consider themselves kings and kingmakers.

    With China’s innovation ...
    by Published on 08-14-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Events
    Article: Mobile SoCs: Two Cores are Better Than Four?-cadence-min.jpg

    Create a panel discussion about analog IC design and reliability and my curiosity is instantly piqued, so I attended a luncheon discussion at #55DAC moderated by Steven Lewis of Cadence. The panelists were quite deep in their specialized fields: ...
    by Published on 08-14-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys,
    4. Artificial Intelligence
    Article: Double Patterning for IC Design, Extraction and Signoff-platform-architect-ultra-ai-min.jpg

    Discussion on machine learning (ML) and hardware design has been picking up significantly in two fascinating areas: how ML can advance hardware design methods and how hardware design methods can advance building ML systems. Here I’ll talk about the latter, particularly about architecting ...
    by Published on 08-13-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. FinFET
    Article: Common Platform Technology Forum February 5th 2013 Live or Online!-caption1.jpg

    The Tale of Three Metrics
    Meeting PPA (Performance, Power and Area) target is key to a successful design tapeout. These mainstream QoR (Quality of Results) metrics are rather empirical yet inter-correlated and have been expanded to be linked with other metrics such as yield, cost and reliability. While the recent CPU performance race is less intense as Moore’s Law ...
    by Published on 08-13-2018 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. IC Knowledge
    Article: Common Platform Technology Forum February 5th 2013 Live or Online!-itf-usa-05-greg-mcintyre-euv-stochastics-challenges-solutions_page_12.jpg

    At SEMICON West I attended the imec technology forum, multiple Tech Spot presentations and conducted a number of interviews relevant to advanced lithography and EUV. In this article I will summarize what I learned plus make some comments on the outlook for EUV.
    ...

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