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    by Published on 06-22-2018 07:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Graphics,
    4. Events
    GSA 3D IC Working Group Meeting | January 23, 2013-dac55-logo.jpg

    It's hard to believe that this is the 55th DAC and even harder to believe that this will be my 35th. So much has changed in 35 years, with DAC back in San Francisco I expect a VERY big crowd and even bigger announcements, absolutely.

    Not only is this an epic time for semiconductors, I would say that EDA is exciting again and the Mentor acquisition by Siemens is definitely a catalyst. Being that this is the first DAC ...
    by Published on 06-22-2018 05:00 AM
    1. Categories:
    2. Wally Rhines
    Which way the semiconductor industry is going?-wally_rhines.jpg

    This is the third in the series of "20 Questions with Wally Rhines":

    In the early 1970s I was working on a PhD thesis based upon GaAs light emitting diodes, or LEDs. Many of my predecessors in the Materials Science and Engineering Department at Stanford had worked on other aspects of III-V compounds ...
    by Published on 06-21-2018 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Mentor Graphics
    Article: Battling SoCs: QCOM vs NVDA vs Samsung-caption.jpg

    Functional and physical verification are easily the two long poles in most IC product developments. During a design implementation cycle, design teams tend to push physical verification (PV) step towards the end as it is a time consuming process and requires significant manual interventions.

    PV Challenges
    In the traditional physical design flow, ...
    by Published on 06-21-2018 10:00 AM
    1. Categories:
    2. Methodics,
    3. Events,
    4. Automotive
    Article: All Things Resistive-methodics-dac.jpg

    I've been visiting DAC for decades now, at first as an EDA vendor and since 2004 as a freelance EDA consultant. There's always a buzz about what's new, semiconductor industry trends, who is getting acquired and the latest commercial EDA and IP offerings. There's so much vying for my attention at DAC each year that it can seem like a blur, however ...
    by Published on 06-21-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. ANSYS, Inc.,
    4. Mobile,
    5. Automotive,
    6. FinFET
    Article: IP vendors enable SuperSpeed USB IP take off in 2012-alaska-fishing-min.jpg

    Iím not going to be at DAC this year because I scheduled a fishing trip at the end of June, assuming the show would stay true to form as an early/mid-June event. Still, having to endure salmon and halibut fishing in Alaska rather than slogging around Moscone ...
    by Published on 06-20-2018 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Events
    CES 2013 Trip Reports (Win an iPad Mini!)-hot-2018-banner-ad-400x400.jpg

    The Design Automation Conference (DAC), now in its 55th year, always offers a lively mix of activities. For EDA vendors and their customers, the focus is on the exhibit floor and in booth suites where the latest technology is on display. For R&D ...
    by Published on 06-20-2018 09:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Oski Technology
    Article: Is the RTL Design Flow Broken?-vigyan-min.jpg

    If you read around topics in advanced formal verification youíre likely to run into something called Wolper coloring, or what Vigyan Singhal (Chief Oski at Oski) calls the Wolper method. Many domains have specialized techniques but whatís surprising in this instance is a seeming absence ...
    by Published on 06-20-2018 04:00 AM  Number of Views: 3471 
    1. Categories:
    2. Semiconductor Manufacturers,
    3. TSMC,
    4. Events,
    5. Open-Silicon
    Article: Is the RTL Design Flow Broken?-tsmc-dac-oip-schedule.jpg

    The TSMC OIP DAC Theater schedule is finalized and ready to go. It kicks off Monday at 10:15 am in booth #1629 and ends with a raffle at 5:45 pm each day (Mon-Tue-Wed) TSMC gives out some very nice prizes so check in with the TSMC booth staff when you arrive. There are 66 coveted presentation spots ...
    by Published on 06-19-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. AnaGlobe
    Article: Is the RTL Design Flow Broken?-fast-read.jpg

    During the design cycle as tape out approaches, time pressure usually goes up dramatically. To make matters worse the design itself is much larger, because all the block level work is done and there is a requirement to work with the entire database. ...
    by Published on 06-19-2018 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. ArterisIP,
    4. Automotive
    Article: Is the RTL Design Flow Broken?-ip-library-fmea-min.jpg

    In the course of building my understanding of functional safety, particularly with respect to ISO 26262, I have developed a better understanding of the design methods used to mitigate safety problems and the various tools and techniques ...

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