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    by Published on 03-20-2019 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    Article: Prediction is very difficult, especially about the future-electronic-system-definition-min.jpg

    Many electronic product ideas start out as sketches on the back of a napkin, then migrate over to diagrams drawn in Visio or PowerPoint, finally entered into EDA-specific tools. With that methodology there's a big disconnect between the diagrams drawn with a purely graphical tool and the EDA tools, because there's no data linkage happening, so there's no consistency and no automation when a change is made to the specification. ...
    by Published on 03-20-2019 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. FPGA,
    5. Synopsys,
    6. ARM
    Article: Functional Check List in Verification-customer-feedback-min.jpeg

    Synopsys runs a “Industry verifies with Synopsys” lunch at each DVCon, which isn’t as cheesy as the title might suggest. The bulk of the lunch covers user presentations on their use of Synopsys tools which I find informative and quite open, sharing problems as much as successes. This year, ...
    by Published on 03-19-2019 10:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. SiFive,
    4. RISC-V
    Article: Intel's x86 - Foundry Breakup Comes into View-si5_12_n.jpg

    During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, ...
    by Published on 03-19-2019 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. ArterisIP,
    4. Sonics,
    5. NetSpeed Systems
    -sonics-facebook-logo.jpg

    What does Qualcomm, Intel, and Facebook have in common? Well, for one thing they all bought network onchip communications (NoC) IP companies. As I have mentioned before, semiconductor IP is the foundation of the fabless semiconductor ecosystem and I believe this trend of ...
    by Published on 03-18-2019 10:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. SiFive,
    4. RISC-V
    Article: SPICE Circuit Simulation at STMicroelectronics-si5_1_n.jpg

    SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of ...
    by Published on 03-18-2019 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Graphics,
    4. Events
    Article: Intel's x86 - Foundry Breakup Comes into View-boeing-373-max-grounded.jpg

    There was an interesting keynote at DVCon last month. It was titled “Thriving in the Age of Digitalization” which introduced the concept of digital twins for design and production. It was presented by Fram Akiki who is a relative newcomer to EDA but has an interesting history ...
    by Published on 03-17-2019 05:00 AM
    1. Categories:
    2. Automotive
    Article: Cadence ♥ ClioSoft!-i-finally-understand-brexit.jpg

    I have gazed across the Pond in bafflement over Brexit until two days ago. I now grasp the depth and breadth of British anxiety over political and legal ties to Brussels and it boils down to regulatory over-reach.

    Yesterday, the European Commission announced that it had adopted new rules “stepping up the deployment of Cooperative Intelligent Transport Systems (C-ITS) on Europe's roads.” What the commission has actually done is to create ...
    by Published on 03-15-2019 05:00 AM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. Events
    Article: TSMC ♥ Cadence-fcmn_2019_800x188.jpg

    On April 2 – 4, the 2019 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN) will be held at the Monterey Marriott in Monterey, CA. The 2019 FCMN is the 12th in the series that began in 1995 with a keynote talk by Craig Barrett, ex-CEO of Intel.

    ...
    by Published on 03-15-2019 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. ESDA Alliance,
    4. Events

    I had a chat with Bob Smith, Executive Director of ESD Alliance, about the upcoming SEMI conference in China. More than 100,000 people are expected to attend which is beyond my comprehension. SEMICON in San Francisco is maybe 20,000 people which is the largest conference I attend. I’m not ...
    by Published on 03-14-2019 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Methodics,
    4. General
    Article: TSMC ♥ Cadence-requirements-design-verification-min.jpg

    The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We've all heard the maxim, "Work smarter, not harder." A white paper just came out from Methodics on a smarter approach, Traceability for the Design Verification Process, so I've taken the time to read the 9 pages and then present my findings. The three activities in ...

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