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    by Published on 12-14-2018 11:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    Article: SemiWiki Hits Major Readership Milestone!-next-generation-formal-verification-1.jpg

    As SoC and IP designs continue to increase in complexity while schedules accelerate, verification teams are looking for methodologies to improve design confidence more quickly. Formal verification techniques provide one route to improved design confidence, and the increase in papers and interest ...
    by Published on 12-14-2018 06:00 AM
    1. Categories:
    2. FPGA,
    3. Achronix,
    4. Artificial Intelligence
    Article: No EUV before 7nm?-why-fpga.jpg

    With their current line-up of embeddable and discrete FPGA products, Achronix has made a big impact on their markets. They started with their Speedster FPGA standard products, and then essentially created a brand-new market for embeddable FPGA IP cores. They have just announced a new ...
    by Published on 12-13-2018 11:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Graphics
    Article: Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!-caption.jpg

    Higher level synthesis (HLS) of an IP block involves taking its high-level design specification –usually captured in SystemC or C++, synthesizes and generates its RTL equivalent. HLS provides a faster convergence path to design code stability, promotes design reuse and lowers front-end design inception cost.

    HLS and Mentor Catapult Platform ...
    by Published on 12-13-2018 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. ANSYS, Inc.
    Article: No EUV before 7nm?-looking-ahead-min.jpeg

    ANSYS recently hosted a webinar talking about how they used the big-data analytics available in RedHawk-SC to do early power grid planning with static analytics, providing better coverage than would have been possible through pure simulation-based ...
    by Published on 12-12-2018 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Events
    Article: Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!-dvcon.jpg

    As 2018 wraps up this month it's time to start thinking and planning for 2019, and if you work in the Silicon Valley then you'll want to consider adding the 31st annual DVCon event planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on ...
    by Published on 12-11-2018 11:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Semiconductor Services,
    4. eSilicon
    Article: 9 Micron Wooden Gate-bandwidth.jpg

    No matter how high the processing capability of a chip, its overall performance is limited by IO speed. This is very similar to a car with low performance tires, a powerful engine will not be able to transfer its energy to the ground effectively. ...
    by Published on 12-11-2018 06:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. IC Knowledge
    Article: Cosmic Circuits acquisition by Cadence: IP battle with Synopsys has officially started!-iedm-2018-yen-presented-version_page_07.jpg

    At IEDM last week Anthony (Tony) Yen, Vice President and Head, Technology Development Centers Worldwide for ASML presented a paper entitled “EUV Lithography at Threshold of High-Volume Manufacturing” authored by Anthony Yen, Hans Meiling, and Jos Benschop. At IEDM I had a chance to sit down with Tony and discuss the paper and the ...
    by Published on 12-10-2018 11:00 AM
    Research Study on Circuit Pads-semiconductor-equipment-top-7.jpg

    Semiconductor equipment vendor ranking, which didn’t change much between 2016 and 2017, is undergoing a makeover, as Lam Research, ASML, and Tokyo Electron (TEL) are switching places and top-ranked Applied Materials is getting closer to losing its number one ranking.

    Since the 1990s, Applied Materials has been the market leader in the semiconductor equipment ...
    by Published on 12-10-2018 06:00 AM
    1. Categories:
    2. Events
    Article: No EUV before 7nm?-iedm-2018.jpg

    Hello, my name is Daniel Nenni and I am a semiconductor conference addict. I just can’t seem to get enough. The semiconductor ecosystem is very wide now and moves so quickly it is nearly impossible to keep up without constant conference attendance. ...
    by Published on 12-10-2018 06:00 AM
    1. Categories:
    2. Automotive
    Tackling large-scale SoC and FPGA prototyping debug challenges-gm-stop-downsizing.jpg

    General Motors CEO Mary Barra is known for a number of quotes one of which is: “My father was a die maker for 39 years, so I had a basic understanding of the automobile industry and what the manufacturing world was like, just from the opportunity to spend time with him, just talking, because he was a car buff.” One has to wonder what Mary’s dad would have so say about the latest news out of GM.

    Two major press ...

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