You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Semiconductor Expert Forum RSS Feed

    by Published on 07-20-2018 10:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Events,
    4. NetSpeed Systems,
    5. Artificial Intelligence
    Article: Mobile SoCs: Two Cores are Better Than Four?-netspeed-ai-soc-webinar.jpg

    Artificial Intelligence is one of the most talked about topics on the conference circuit this year and I don’t expect that to change anytime soon. AI is also one of the trending topics on SemiWiki with organic search bringing us a wealth of new viewers. You may also have noticed that AI is a hot topic for webinars ...
    by Published on 07-20-2018 05:00 AM
    1. Categories:
    2. Wally Rhines
    Article: All Things Resistive-ti-silent-700-portable-terminal.jpg

    This is the seventh in the series of "20 Questions with Wally Rhines"

    Probably the most innovative person I met at Texas Instruments, other than Jack Kilby, was Ken Bean. Ken had a list of patents that would impress even ...
    by Published on 07-19-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Avatar Integrated Systems
    Article: What did CES 2013 mean for #SemiEDA?-caption1.jpg

    Earlier physical optimization impacts a design QoR gain and can disclose potential hurdles in dealing with unknown design variants such as new IP inclusion or new process node issues. Along the RTL-to-GDS2 implementation continuum, a left-shift move requires a robust modeling and proper context captures in order to produce meaningful outcomes.

    Aside from ...
    by Published on 07-19-2018 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. ArterisIP
    Article: TSMC Apple Rumors Debunked!-caches-soc-min.jpg

    We tend to think of cache primarily as an adjunct to processors to improve performance. Reading and writing main memory (DRAM) is very slow thanks to all the package and board impedance between chips. If you can fetch blocks of contiguous memory from the DRAM ...
    by Published on 07-18-2018 10:00 AM
    1. Categories:
    2. Flex Logix
    Article: Cadence, Synopsys, and Mentor on FinFETs-network-graph.png

    Machine learning-based applications have become prevalent across consumer, medical, and automotive markets. Still, the underlying architecture(s) and implementations are evolving rapidly, to best fit the throughput, latency, and power efficiency requirements of an ever increasing application space. Although ML is often associated with the unique nature of (many parallel) compute engines in GPU hardware, the opportunities for ML designs extend to cost-sensitive, low-power markets. The implementation of an ML ...
    by Published on 07-18-2018 05:00 AM
    1. Categories:
    2. Semiconductor Manufacturers,
    3. GlobalFoundries,
    4. Intel,
    5. Events
    -7nm-intel-tsmc-samsung.jpg

    SEMICON West seemed a little slow last week but maybe it was just me. I’m sure SEMI will come out with record breaking numbers but I did not see it in the exhibit hall (see the video). What I did see was hundreds of exhibitors but I had no idea what they did. San Francisco ...
    by Published on 07-17-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys,
    4. Events
    Article: Oasys Has a New CEO-caption1.jpg

    At DAC 2018, Synopsys held a lunch panel discussing verification challenges faced by the industry leaders, their adopted approaches and the overall verification technology trends. This panel of industry experts from Intel, AMD, Samsung, STM and Qualcomm also shared their viewpoints on what drives the SoC complexity and how their teams have tackled them and achieved successes.

    From the Synopsys ...
    by Published on 07-17-2018 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. eSilicon,
    4. Artificial Intelligence
    -efficiency-asic-min.jpg

    There is a well-known progression in the efficiency of different platforms for certain targeted applications such as AI, as measured by performance and performance/Watt. The progression is determined by how much of the application can be run with specialized hardware-assist rather than software, ...
    by Published on 07-16-2018 10:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. Semiconductor Advisors
    Article: Cadence, Synopsys, and Mentor on FinFETs-0_vlsi_2018_cfet_julien-ryckaert_page_02.jpg

    The 2018 VLSI Technology conference was held in Hawaii in June and is one of the premier conferences covering integrated circuit process technology and circuit design. The Complementary FET (CFET) is an emerging option to continue logic scaling into the next decade. At the conference imec, GLOBALFOUNDRIES, Tokyo Electron and Coventor presented “The Complementary FET (CFET) for ...
    by Published on 07-12-2018 05:00 AM
    1. Categories:
    2. Artificial Intelligence
    Article: Cadence, Synopsys, and Mentor on FinFETs-deep-learning-jul-2018-min.jpeg

    Deep learning (DL) has become the oracle of our age – the universal technology we turn to for answers to almost any hard problem. This is not surprising; its strength in image and speech recognition, language processing and multiple other domains amaze and shock us, to the point that we’re now debating AI singularities. ...

    Page 1 of 10 1 2 3 4 5 6 7