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    by Published on 09-20-2017 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cliosoft,
    4. IoT Internet of Things
    Article: Variation-Aware Design: A Hands-on Field Guide-designhub-min-jpg

    Design data management has always been important. Board designers have known this for decades as they had to have ways to keep all their discreet components organized and understood. Sourcing components is not easy as it means hours of reading and reviewing specifications, ...
    by Published on 09-20-2017 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Semitracks
    Article: Double Patterning Exposed!-wafer-map-low-yield-jpg

    One of the most important aspects of any manufacturing effort is the yield of the process. Today, the investment in facilities, equipment and materials is so high that consistently high yields are ...
    by Published on 09-19-2017 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. FinFET
    Article: How Apple Plans to Leverage Intel's Foundry-sia-min-jpg

    My IC design career started out with DRAM design, characterization and verification back in the 1970's, so I vividly recall how much SPICE circuit simulation was involved, and how little automation we had back in the day, so we tended to cobble together our own scripts to help automate the process a bit. With each ...
    by Published on 09-19-2017 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec
    Article: How Apple Plans to Leverage Intel's Foundry-aldec-hes-min-jpg

    I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end ...
    by Published on 09-18-2017 10:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Semiconductor Advisors
    Article: Double Patterning Exposed!-lattice-semiconductor-jpg

    Although the rejection of the Lattice deal was expected, it none the less has an impact on a number of dynamics in the chip industry and further M&A and consolidation. Freezing out China removes a "catalyst" in the market which help bid up values and add fear to both potential targets or those left out. Cross border deals are obviously more difficult to get done and even small deals with China will likely be put under a microscope now.

    The Xcerra deal is likely very safe given ...
    by Published on 09-18-2017 05:00 AM
    1. Categories:
    2. Semiconductor Design
    Article: How Apple Plans to Leverage Intel's Foundry-atoptech-logo-png

    One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly ...
    by Published on 09-17-2017 03:00 PM
    1. Categories:
    2. General
    Article: How Apple Plans to Leverage Intel's Foundry-brcair-min-jpg

    I often use this space to report on industry events I have attended and what I have learned at them. So, this article will be a slight, but not complete, departure from this. I am reporting on my experiences at Burning Man this year. For the unacquainted, Burning Man is a temporary city of around 70,000 people in a remote desert-like dry lake bed in Northern Nevada. The Black ...
    by Published on 09-15-2017 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Graphics,
    4. Automotive
    Article: Improving FPGA Prototype Debugging-bosch-min-jpg

    Some of the world’s most complex Systems-on-Chip (SoCs) are being developed for automotive applications. These SoCs have heterogeneous architectures with a variety of processors and accelerators that do real-time image processing for assisted and autonomous driving applications. ...
    by Published on 09-14-2017 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. ANSYS, Inc.
    Article: Embedding 100K probes in FPGA-based prototypes-power-noise-management-3dic-min-jpg

    The semiconductor industry has built decades of success on hyper-integration to increase functionality and performance while also reducing system cost. But the standard way to do this, to jam more and more functionality onto a single die, breaks down when some of ...
    by Published on 09-13-2017 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Events,
    4. FinFET,
    5. Platform Design Automation
    Article: Challenges of Implementing LTE-pda-dac-min-jpg

    One of my favorite classes in college was the lab exercise, mostly because we actually got to use real electronics and then measure something, finally writing it up in our lab notebooks. The issue today is that a college student taking Electrical Engineering probably doesn't have much access to 10nm FinFET silicon for use in a lab class, and they are probably using really out of date materials and lab exercises. At the DAC exhibit in ...

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